#define FPU_VFP_EXT_V3 0
#define FPU_NEON_EXT_V1 0
-int floatformat_ieee_single_little;
/* Assume host uses ieee float. */
-static void floatformat_to_double (int *ignored, unsigned char *data,
- double *dest)
+static void floatformat_to_double (unsigned char *data, double *dest)
{
union {
uint32_t i;
}
static void
-arm_decode_shift (long given, fprintf_ftype func, void *stream,
+arm_decode_shift (long given, fprintf_function func, void *stream,
int print_shift)
{
func (stream, "%s", arm_regnames[given & 0xf]);
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_function func = info->fprintf_func;
unsigned long mask;
unsigned long value;
int cond;
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_function func = info->fprintf_func;
if (((given & 0x000f0000) == 0x000f0000)
&& ((given & 0x02000000) == 0))
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_function func = info->fprintf_func;
if (thumb)
{
{
func (stream, "<illegal constant %.8x:%x:%x>",
bits, cmode, op);
- size = 32;
break;
}
switch (size)
valbytes[2] = (value >> 16) & 0xff;
valbytes[3] = (value >> 24) & 0xff;
- floatformat_to_double
- (&floatformat_ieee_single_little, valbytes,
- &fvalue);
+ floatformat_to_double (valbytes, &fvalue);
func (stream, "#%.7g\t; 0x%.8lx", fvalue,
value);
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_function func = info->fprintf_func;
if (print_insn_coprocessor (pc, info, given, false))
return;
{
const struct opcode16 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_function func = info->fprintf_func;
for (insn = thumb_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
if (started)
func (stream, ", ");
started = 1;
- func (stream, arm_regnames[14] /* "lr" */);
+ func (stream, "%s", arm_regnames[14] /* "lr" */);
}
if (domaskpc)
{
if (started)
func (stream, ", ");
- func (stream, arm_regnames[15] /* "pc" */);
+ func (stream, "%s", arm_regnames[15] /* "pc" */);
}
func (stream, "}");
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_function func = info->fprintf_func;
if (print_insn_coprocessor (pc, info, given, true))
return;
}
else
{
- func (stream, psr_name (given & 0xff));
+ func (stream, "%s", psr_name (given & 0xff));
}
break;
if ((given & 0xff) == 0)
func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
else
- func (stream, psr_name (given & 0xff));
+ func (stream, "%s", psr_name (given & 0xff));
break;
case '0': case '1': case '2': case '3': case '4':
addresses, since the addend is not currently pc-relative. */
pc = 0;
+ /* We include the hexdump of the instruction. The format here
+ matches that used by objdump and the ARM ARM (in particular,
+ 32 bit Thumb instructions are displayed as pairs of halfwords,
+ not as a single word.) */
+ if (is_thumb)
+ {
+ if (size == 2)
+ {
+ info->fprintf_func(info->stream, "%04lx ",
+ ((unsigned long)given) & 0xffff);
+ }
+ else
+ {
+ info->fprintf_func(info->stream, "%04lx %04lx ",
+ (((unsigned long)given) >> 16) & 0xffff,
+ ((unsigned long)given) & 0xffff);
+ }
+ }
+ else
+ {
+ info->fprintf_func(info->stream, "%08lx ",
+ ((unsigned long)given) & 0xffffffff);
+ }
+
printer (pc, info, given);
if (is_thumb)