#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "kvm.h"
//#define DEBUG_VGA
//#define DEBUG_VGA_MEM
static uint16_t expand2[256];
static uint8_t expand4to8[16];
-typedef VGACommonState VGAState;
-
static void vga_screen_dump(void *opaque, const char *filename);
static char *screen_dump_filename;
static DisplayChangeListener *screen_dump_dcl;
-static void vga_dumb_update_retrace_info(VGAState *s)
+static void vga_dumb_update_retrace_info(VGACommonState *s)
{
(void) s;
}
-static void vga_precise_update_retrace_info(VGAState *s)
+static void vga_precise_update_retrace_info(VGACommonState *s)
{
int htotal_chars;
int hretr_start_char;
int vretr_start_line;
int vretr_end_line;
- int div2, sldiv2, dots;
+ int dots;
+#if 0
+ int div2, sldiv2;
+#endif
int clocking_mode;
int clock_sel;
const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
vretr_end_line = s->cr[0x11] & 0xf;
- div2 = (s->cr[0x17] >> 2) & 1;
- sldiv2 = (s->cr[0x17] >> 3) & 1;
clocking_mode = (s->sr[0x01] >> 3) & 1;
clock_sel = (s->msr >> 2) & 3;
r->total_chars = vtotal_lines * htotal_chars;
if (r->freq) {
- r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
+ r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
} else {
- r->ticks_per_char = ticks_per_sec / chars_per_sec;
+ r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
}
r->vstart = vretr_start_line;
r->htotal = htotal_chars;
#if 0
+ div2 = (s->cr[0x17] >> 2) & 1;
+ sldiv2 = (s->cr[0x17] >> 3) & 1;
printf (
"hz=%f\n"
"htotal = %d\n"
"clocking_mode = %d\n"
"clock_sel = %d %d\n"
"dots = %d\n"
- "ticks/char = %lld\n"
+ "ticks/char = %" PRId64 "\n"
"\n",
- (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
+ (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
htotal_chars,
hretr_start_char,
hretr_skew_chars,
#endif
}
-static uint8_t vga_precise_retrace(VGAState *s)
+static uint8_t vga_precise_retrace(VGACommonState *s)
{
struct vga_precise_retrace *r = &s->retrace_info.precise;
uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
int cur_line, cur_line_char, cur_char;
int64_t cur_tick;
- cur_tick = qemu_get_clock(vm_clock);
+ cur_tick = qemu_get_clock_ns(vm_clock);
cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
cur_line = cur_char / r->htotal;
}
}
-static uint8_t vga_dumb_retrace(VGAState *s)
+static uint8_t vga_dumb_retrace(VGACommonState *s)
{
return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
}
+int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
+{
+ if (s->msr & MSR_COLOR_EMULATION) {
+ /* Color */
+ return (addr >= 0x3b0 && addr <= 0x3bf);
+ } else {
+ /* Monochrome */
+ return (addr >= 0x3d0 && addr <= 0x3df);
+ }
+}
+
uint32_t vga_ioport_read(void *opaque, uint32_t addr)
{
VGACommonState *s = opaque;
int val, index;
- /* check port range access depending on color/monochrome mode */
- if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
- (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
+ if (vga_ioport_invalid(s, addr)) {
val = 0xff;
} else {
switch(addr) {
case 0x3c7:
val = s->dac_state;
break;
- case 0x3c8:
- val = s->dac_write_index;
- break;
+ case 0x3c8:
+ val = s->dac_write_index;
+ break;
case 0x3c9:
val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
if (++s->dac_sub_index == 3) {
int index;
/* check port range access depending on color/monochrome mode */
- if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
- (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
+ if (vga_ioport_invalid(s, addr)) {
return;
-
+ }
#ifdef DEBUG_VGA
printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
#endif
s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
return;
}
- switch(s->cr_index) {
- case 0x01: /* horizontal display end */
- case 0x07:
- case 0x09:
- case 0x0c:
- case 0x0d:
- case 0x12: /* vertical display end */
- s->cr[s->cr_index] = val;
- break;
- default:
- s->cr[s->cr_index] = val;
- break;
- }
+ s->cr[s->cr_index] = val;
switch(s->cr_index) {
case 0x00:
#ifdef CONFIG_BOCHS_VBE
static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
uint32_t val;
val = s->vbe_index;
return val;
static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
uint32_t val;
- if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
+ if (s->vbe_index < VBE_DISPI_INDEX_NB) {
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
switch(s->vbe_index) {
/* XXX: do not hardcode ? */
} else {
val = s->vbe_regs[s->vbe_index];
}
+ } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
+ val = s->vram_size / (64 * 1024);
} else {
val = 0;
}
static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
s->vbe_index = val;
}
static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
#ifdef DEBUG_BOCHS_VBE
/* called for accesses between 0xa0000 and 0xc0000 */
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
int memory_map_mode, plane;
uint32_t ret;
static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = vga_mem_readb(opaque, addr) << 8;
- v |= vga_mem_readb(opaque, addr + 1);
-#else
v = vga_mem_readb(opaque, addr);
v |= vga_mem_readb(opaque, addr + 1) << 8;
-#endif
return v;
}
static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = vga_mem_readb(opaque, addr) << 24;
- v |= vga_mem_readb(opaque, addr + 1) << 16;
- v |= vga_mem_readb(opaque, addr + 2) << 8;
- v |= vga_mem_readb(opaque, addr + 3);
-#else
v = vga_mem_readb(opaque, addr);
v |= vga_mem_readb(opaque, addr + 1) << 8;
v |= vga_mem_readb(opaque, addr + 2) << 16;
v |= vga_mem_readb(opaque, addr + 3) << 24;
-#endif
return v;
}
/* called for accesses between 0xa0000 and 0xc0000 */
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
int memory_map_mode, plane, write_mode, b, func_select, mask;
uint32_t write_mask, bit_mask, set_mask;
static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
- vga_mem_writeb(opaque, addr + 1, val & 0xff);
-#else
vga_mem_writeb(opaque, addr, val & 0xff);
vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-#endif
}
static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
- vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
- vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
- vga_mem_writeb(opaque, addr + 3, val & 0xff);
-#else
vga_mem_writeb(opaque, addr, val & 0xff);
vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-#endif
}
typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
const uint8_t *font_ptr, int h,
uint32_t fgcol, uint32_t bgcol, int dup9);
-typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
+typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
const uint8_t *s, int width);
#define DEPTH 8
}
/* return true if the palette was modified */
-static int update_palette16(VGAState *s)
+static int update_palette16(VGACommonState *s)
{
int full_update, i;
uint32_t v, col, *palette;
}
/* return true if the palette was modified */
-static int update_palette256(VGAState *s)
+static int update_palette256(VGACommonState *s)
{
int full_update, i;
uint32_t v, col, *palette;
return full_update;
}
-static void vga_get_offsets(VGAState *s,
+static void vga_get_offsets(VGACommonState *s,
uint32_t *pline_offset,
uint32_t *pstart_addr,
uint32_t *pline_compare)
}
/* update start_addr and line_offset. Return TRUE if modified */
-static int update_basic_params(VGAState *s)
+static int update_basic_params(VGACommonState *s)
{
int full_update;
uint32_t start_addr, line_offset, line_compare;
}
}
-static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
+static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
vga_draw_glyph8_8,
vga_draw_glyph8_16,
vga_draw_glyph8_16,
vga_draw_glyph8_16,
};
-static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
+static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
vga_draw_glyph16_8,
vga_draw_glyph16_16,
vga_draw_glyph16_16,
vga_draw_glyph16_16,
};
-static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
+static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
vga_draw_glyph9_8,
vga_draw_glyph9_16,
vga_draw_glyph9_16,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
-static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
+static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
int *pcwidth, int *pcheight)
{
int width, cwidth, height, cheight;
typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
-static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
+static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
rgb_to_pixel8_dup,
rgb_to_pixel15_dup,
rgb_to_pixel16_dup,
* - underline
* - flashing
*/
-static void vga_draw_text(VGAState *s, int full_update)
+static void vga_draw_text(VGACommonState *s, int full_update)
{
int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
- int cx_min, cx_max, linesize, x_incr;
+ int cx_min, cx_max, linesize, x_incr, line, line1;
uint32_t offset, fgcol, bgcol, v, cursor_offset;
- uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
+ uint8_t *d1, *d, *src, *dest, *cursor_ptr;
const uint8_t *font_ptr, *font_base[2];
int dup9, line_offset, depth_index;
uint32_t *palette;
full_update |= update_basic_params(s);
line_offset = s->line_offset;
- s1 = s->vram_ptr + (s->start_addr * 4);
vga_get_text_resolution(s, &width, &height, &cw, &cheight);
- x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
if ((height * width) > CH_ATTR_SIZE) {
/* better than nothing: exit if transient size is too big */
return;
dest = ds_get_data(s->ds);
linesize = ds_get_linesize(s->ds);
ch_attr_ptr = s->last_ch_attr;
+ line = 0;
+ offset = s->start_addr * 4;
for(cy = 0; cy < height; cy++) {
d1 = dest;
- src = s1;
+ src = s->vram_ptr + offset;
cx_min = width;
cx_max = -1;
for(cx = 0; cx < width; cx++) {
(cx_max - cx_min + 1) * cw, cheight);
}
dest += linesize * cheight;
- s1 += line_offset;
+ line1 = line + cheight;
+ offset += line_offset;
+ if (line < s->line_compare && line1 >= s->line_compare) {
+ offset = 0;
+ }
+ line = line1;
}
}
VGA_DRAW_LINE_NB,
};
-static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
+static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
vga_draw_line2_8,
vga_draw_line2_16,
vga_draw_line2_16,
vga_draw_line32_16bgr,
};
-static int vga_get_bpp(VGAState *s)
+static int vga_get_bpp(VGACommonState *s)
{
int ret;
#ifdef CONFIG_BOCHS_VBE
return ret;
}
-static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
+static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
{
int width, height;
*pheight = height;
}
-void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
+void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
{
int y;
if (y1 >= VGA_MAX_HEIGHT)
}
}
-static void vga_sync_dirty_bitmap(VGAState *s)
+static void vga_sync_dirty_bitmap(VGACommonState *s)
{
if (s->map_addr)
cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
}
+
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_mapped) {
+ cpu_physical_sync_dirty_bitmap(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
+ VBE_DISPI_LFB_PHYSICAL_ADDRESS + s->vram_size);
+ }
+#endif
+
+}
+
+void vga_dirty_log_start(VGACommonState *s)
+{
+ if (s->map_addr) {
+ cpu_physical_log_start(s->map_addr, s->map_end - s->map_addr);
+ }
+
+ if (s->lfb_vram_mapped) {
+ cpu_physical_log_start(isa_mem_base + 0xa0000, 0x8000);
+ cpu_physical_log_start(isa_mem_base + 0xa8000, 0x8000);
+ }
+
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_mapped) {
+ cpu_physical_log_start(VBE_DISPI_LFB_PHYSICAL_ADDRESS, s->vram_size);
+ }
+#endif
+}
+
+void vga_dirty_log_stop(VGACommonState *s)
+{
+ if (s->map_addr) {
+ cpu_physical_log_stop(s->map_addr, s->map_end - s->map_addr);
+ }
+
+ if (s->lfb_vram_mapped) {
+ cpu_physical_log_stop(isa_mem_base + 0xa0000, 0x8000);
+ cpu_physical_log_stop(isa_mem_base + 0xa8000, 0x8000);
+ }
+
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_mapped) {
+ cpu_physical_log_stop(VBE_DISPI_LFB_PHYSICAL_ADDRESS, s->vram_size);
+ }
+#endif
+}
+
+void vga_dirty_log_restart(VGACommonState *s)
+{
+ vga_dirty_log_stop(s);
+ vga_dirty_log_start(s);
}
/*
* graphic modes
*/
-static void vga_draw_graphic(VGAState *s, int full_update)
+static void vga_draw_graphic(VGACommonState *s, int full_update)
{
int y1, y, update, linesize, y_start, double_scan, mask, depth;
int width, height, shift_control, line_offset, bwidth, bits;
memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
}
-static void vga_draw_blank(VGAState *s, int full_update)
+static void vga_draw_blank(VGACommonState *s, int full_update)
{
int i, w, val;
uint8_t *d;
static void vga_update_display(void *opaque)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
int full_update, graphic_mode;
if (ds_get_bits_per_pixel(s->ds) == 0) {
/* nothing to do */
} else {
- full_update = s->full_update;
- s->full_update = 0;
+ full_update = 0;
if (!(s->ar_index & 0x20)) {
graphic_mode = GMODE_BLANK;
} else {
/* force a full display refresh */
static void vga_invalidate_display(void *opaque)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
- s->full_update = 1;
+ s->last_width = -1;
+ s->last_height = -1;
}
void vga_common_reset(VGACommonState *s)
s->map_addr = 0;
s->map_end = 0;
s->lfb_vram_mapped = 0;
- s->bios_offset = 0;
- s->bios_size = 0;
s->sr_index = 0;
memset(s->sr, '\0', sizeof(s->sr));
s->gr_index = 0;
#ifdef CONFIG_BOCHS_VBE
s->vbe_index = 0;
memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
- s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
+ s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
s->vbe_start_addr = 0;
s->vbe_line_offset = 0;
s->vbe_bank_mask = (s->vram_size >> 16) - 1;
static void vga_reset(void *opaque)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
vga_common_reset(s);
}
* instead of doing a full vga_update_display() */
static void vga_update_text(void *opaque, console_ch_t *chardata)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
int graphic_mode, i, cursor_offset, cursor_visible;
int cw, cheight, width, height, size, c_min, c_max;
uint32_t *src;
if (full_update) {
for (i = 0; i < size; src ++, dst ++, i ++)
- console_write_ch(dst, VMEM2CHTYPE(*src));
+ console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
dpy_update(s->ds, 0, 0, width, height);
} else {
c_max = 0;
for (i = 0; i < size; src ++, dst ++, i ++) {
- console_write_ch(&val, VMEM2CHTYPE(*src));
+ console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
if (*dst != val) {
*dst = val;
c_max = i;
}
c_min = i;
for (; i < size; src ++, dst ++, i ++) {
- console_write_ch(&val, VMEM2CHTYPE(*src));
+ console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
if (*dst != val) {
*dst = val;
c_max = i;
dpy_update(s->ds, 0, 0, s->last_width, height);
}
-static CPUReadMemoryFunc * const vga_mem_read[3] = {
+CPUReadMemoryFunc * const vga_mem_read[3] = {
vga_mem_readb,
vga_mem_readw,
vga_mem_readl,
};
-static CPUWriteMemoryFunc * const vga_mem_write[3] = {
+CPUWriteMemoryFunc * const vga_mem_write[3] = {
vga_mem_writeb,
vga_mem_writew,
vga_mem_writel,
};
-static void vga_save(QEMUFile *f, void *opaque)
-{
- VGAState *s = opaque;
- int i;
-
- if (s->pci_dev)
- pci_device_save(s->pci_dev, f);
-
- qemu_put_be32s(f, &s->latch);
- qemu_put_8s(f, &s->sr_index);
- qemu_put_buffer(f, s->sr, 8);
- qemu_put_8s(f, &s->gr_index);
- qemu_put_buffer(f, s->gr, 16);
- qemu_put_8s(f, &s->ar_index);
- qemu_put_buffer(f, s->ar, 21);
- qemu_put_be32(f, s->ar_flip_flop);
- qemu_put_8s(f, &s->cr_index);
- qemu_put_buffer(f, s->cr, 256);
- qemu_put_8s(f, &s->msr);
- qemu_put_8s(f, &s->fcr);
- qemu_put_byte(f, s->st00);
- qemu_put_8s(f, &s->st01);
-
- qemu_put_8s(f, &s->dac_state);
- qemu_put_8s(f, &s->dac_sub_index);
- qemu_put_8s(f, &s->dac_read_index);
- qemu_put_8s(f, &s->dac_write_index);
- qemu_put_buffer(f, s->dac_cache, 3);
- qemu_put_buffer(f, s->palette, 768);
-
- qemu_put_be32(f, s->bank_offset);
-#ifdef CONFIG_BOCHS_VBE
- qemu_put_byte(f, 1);
- qemu_put_be16s(f, &s->vbe_index);
- for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
- qemu_put_be16s(f, &s->vbe_regs[i]);
- qemu_put_be32s(f, &s->vbe_start_addr);
- qemu_put_be32s(f, &s->vbe_line_offset);
- qemu_put_be32s(f, &s->vbe_bank_mask);
-#else
- qemu_put_byte(f, 0);
-#endif
-}
-
-static int vga_load(QEMUFile *f, void *opaque, int version_id)
+static int vga_common_post_load(void *opaque, int version_id)
{
- VGAState *s = opaque;
- int is_vbe, i, ret;
-
- if (version_id > 2)
- return -EINVAL;
-
- if (s->pci_dev && version_id >= 2) {
- ret = pci_device_load(s->pci_dev, f);
- if (ret < 0)
- return ret;
- }
-
- qemu_get_be32s(f, &s->latch);
- qemu_get_8s(f, &s->sr_index);
- qemu_get_buffer(f, s->sr, 8);
- qemu_get_8s(f, &s->gr_index);
- qemu_get_buffer(f, s->gr, 16);
- qemu_get_8s(f, &s->ar_index);
- qemu_get_buffer(f, s->ar, 21);
- s->ar_flip_flop=qemu_get_be32(f);
- qemu_get_8s(f, &s->cr_index);
- qemu_get_buffer(f, s->cr, 256);
- qemu_get_8s(f, &s->msr);
- qemu_get_8s(f, &s->fcr);
- qemu_get_8s(f, &s->st00);
- qemu_get_8s(f, &s->st01);
-
- qemu_get_8s(f, &s->dac_state);
- qemu_get_8s(f, &s->dac_sub_index);
- qemu_get_8s(f, &s->dac_read_index);
- qemu_get_8s(f, &s->dac_write_index);
- qemu_get_buffer(f, s->dac_cache, 3);
- qemu_get_buffer(f, s->palette, 768);
-
- s->bank_offset=qemu_get_be32(f);
- is_vbe = qemu_get_byte(f);
-#ifdef CONFIG_BOCHS_VBE
- if (!is_vbe)
- return -EINVAL;
- qemu_get_be16s(f, &s->vbe_index);
- for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
- qemu_get_be16s(f, &s->vbe_regs[i]);
- qemu_get_be32s(f, &s->vbe_start_addr);
- qemu_get_be32s(f, &s->vbe_line_offset);
- qemu_get_be32s(f, &s->vbe_bank_mask);
-#else
- if (is_vbe)
- return -EINVAL;
-#endif
+ VGACommonState *s = opaque;
/* force refresh */
s->graphic_mode = -1;
return 0;
}
-typedef struct PCIVGAState {
- PCIDevice dev;
- VGAState vga;
-} PCIVGAState;
-
-void vga_dirty_log_start(VGAState *s)
-{
- if (kvm_enabled() && s->map_addr)
- kvm_log_start(s->map_addr, s->map_end - s->map_addr);
-
- if (kvm_enabled() && s->lfb_vram_mapped) {
- kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
- kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
- }
-}
-
-static void vga_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
-{
- PCIVGAState *d = (PCIVGAState *)pci_dev;
- VGAState *s = &d->vga;
- if (region_num == PCI_ROM_SLOT) {
- cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
- } else {
- cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
- s->map_addr = addr;
- s->map_end = addr + s->vram_size;
- vga_dirty_log_start(s);
+const VMStateDescription vmstate_vga_common = {
+ .name = "vga",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
+ .post_load = vga_common_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(latch, VGACommonState),
+ VMSTATE_UINT8(sr_index, VGACommonState),
+ VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
+ VMSTATE_UINT8(gr_index, VGACommonState),
+ VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
+ VMSTATE_UINT8(ar_index, VGACommonState),
+ VMSTATE_BUFFER(ar, VGACommonState),
+ VMSTATE_INT32(ar_flip_flop, VGACommonState),
+ VMSTATE_UINT8(cr_index, VGACommonState),
+ VMSTATE_BUFFER(cr, VGACommonState),
+ VMSTATE_UINT8(msr, VGACommonState),
+ VMSTATE_UINT8(fcr, VGACommonState),
+ VMSTATE_UINT8(st00, VGACommonState),
+ VMSTATE_UINT8(st01, VGACommonState),
+
+ VMSTATE_UINT8(dac_state, VGACommonState),
+ VMSTATE_UINT8(dac_sub_index, VGACommonState),
+ VMSTATE_UINT8(dac_read_index, VGACommonState),
+ VMSTATE_UINT8(dac_write_index, VGACommonState),
+ VMSTATE_BUFFER(dac_cache, VGACommonState),
+ VMSTATE_BUFFER(palette, VGACommonState),
+
+ VMSTATE_INT32(bank_offset, VGACommonState),
+ VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
+#ifdef CONFIG_BOCHS_VBE
+ VMSTATE_UINT16(vbe_index, VGACommonState),
+ VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
+ VMSTATE_UINT32(vbe_start_addr, VGACommonState),
+ VMSTATE_UINT32(vbe_line_offset, VGACommonState),
+ VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
+#endif
+ VMSTATE_END_OF_LIST()
}
-}
+};
void vga_common_init(VGACommonState *s, int vga_ram_size)
{
expand4to8[i] = v;
}
- s->vram_offset = qemu_ram_alloc(vga_ram_size);
+#ifdef CONFIG_BOCHS_VBE
+ s->is_vbe_vmstate = 1;
+#else
+ s->is_vbe_vmstate = 0;
+#endif
+ s->vram_offset = qemu_ram_alloc(NULL, "vga.vram", vga_ram_size);
s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
s->vram_size = vga_ram_size;
s->get_bpp = vga_get_bpp;
s->update_retrace_info = vga_precise_update_retrace_info;
break;
}
- vga_reset(s);
}
/* used by both ISA and PCI */
-void vga_init(VGAState *s)
+int vga_init_io(VGACommonState *s)
{
- int vga_io_memory;
-
- qemu_register_reset(vga_reset, s);
- register_savevm("vga", 0, 2, vga_save, vga_load, s);
-
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
- s->bank_offset = 0;
#ifdef CONFIG_BOCHS_VBE
#if defined (TARGET_I386)
register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
-
- /* old Bochs IO ports */
- register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
- register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
-
- register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
- register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
#else
register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
#endif
#endif /* CONFIG_BOCHS_VBE */
- vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
- cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
- vga_io_memory);
- qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
-}
-
-/* Memory mapped interface */
-static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
-{
- VGAState *s = opaque;
-
- return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
-}
-
-static void vga_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- VGAState *s = opaque;
-
- vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
-}
-
-static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
-{
- VGAState *s = opaque;
-
- return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
-}
-
-static void vga_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- VGAState *s = opaque;
-
- vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
+ return cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
+ DEVICE_LITTLE_ENDIAN);
}
-static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
-{
- VGAState *s = opaque;
-
- return vga_ioport_read(s, addr >> s->it_shift);
-}
-
-static void vga_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- VGAState *s = opaque;
-
- vga_ioport_write(s, addr >> s->it_shift, value);
-}
-
-static CPUReadMemoryFunc * const vga_mm_read_ctrl[] = {
- &vga_mm_readb,
- &vga_mm_readw,
- &vga_mm_readl,
-};
-
-static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = {
- &vga_mm_writeb,
- &vga_mm_writew,
- &vga_mm_writel,
-};
-
-static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+void vga_init(VGACommonState *s)
{
- int s_ioport_ctrl, vga_io_memory;
-
- s->it_shift = it_shift;
- s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);
- vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
+ int vga_io_memory;
- register_savevm("vga", 0, 2, vga_save, vga_load, s);
+ qemu_register_reset(vga_reset, s);
- cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
s->bank_offset = 0;
- cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
- qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
-}
-
-int isa_vga_init(void)
-{
- VGAState *s;
- s = qemu_mallocz(sizeof(VGAState));
-
- vga_common_init(s, VGA_RAM_SIZE);
- vga_init(s);
-
- s->ds = graphic_console_init(s->update, s->invalidate,
- s->screen_dump, s->text_update, s);
-
-#ifdef CONFIG_BOCHS_VBE
- /* XXX: use optimized standard vga accesses */
- cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
- VGA_RAM_SIZE, s->vram_offset);
-#endif
- return 0;
+ vga_io_memory = vga_init_io(s);
+ cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
+ vga_io_memory);
+ qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
}
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+void vga_init_vbe(VGACommonState *s)
{
- VGAState *s;
-
- s = qemu_mallocz(sizeof(VGAState));
-
- vga_common_init(s, VGA_RAM_SIZE);
- vga_mm_init(s, vram_base, ctrl_base, it_shift);
-
- s->ds = graphic_console_init(s->update, s->invalidate,
- s->screen_dump, s->text_update, s);
-
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
VGA_RAM_SIZE, s->vram_offset);
-#endif
- return 0;
-}
-
-static void pci_vga_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
-{
- PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
- VGAState *s = &pvs->vga;
-
- pci_default_write_config(d, address, val, len);
- if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
- s->map_addr = 0;
-}
-
-static int pci_vga_initfn(PCIDevice *dev)
-{
- PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
- VGAState *s = &d->vga;
- uint8_t *pci_conf = d->dev.config;
-
- // vga + console init
- vga_common_init(s, VGA_RAM_SIZE);
- vga_init(s);
- s->pci_dev = &d->dev;
- s->ds = graphic_console_init(s->update, s->invalidate,
- s->screen_dump, s->text_update, s);
-
- // dummy VGA (same as Bochs ID)
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
- pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- /* XXX: VGA_RAM_SIZE must be a power of two */
- pci_register_bar(&d->dev, 0, VGA_RAM_SIZE,
- PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
-
- if (s->bios_size) {
- unsigned int bios_total_size;
- /* must be a power of two */
- bios_total_size = 1;
- while (bios_total_size < s->bios_size)
- bios_total_size <<= 1;
- pci_register_bar(&d->dev, PCI_ROM_SLOT, bios_total_size,
- PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
- }
- return 0;
-}
-
-int pci_vga_init(PCIBus *bus,
- unsigned long vga_bios_offset, int vga_bios_size)
-{
- PCIDevice *dev;
-
- dev = pci_create("VGA", NULL);
- qdev_prop_set_uint32(&dev->qdev, "bios-offset", vga_bios_offset);
- qdev_prop_set_uint32(&dev->qdev, "bios-size", vga_bios_offset);
- qdev_init(&dev->qdev);
-
- return 0;
+ s->vbe_mapped = 1;
+#endif
}
-
-static PCIDeviceInfo vga_info = {
- .qdev.name = "VGA",
- .qdev.size = sizeof(PCIVGAState),
- .init = pci_vga_initfn,
- .config_write = pci_vga_write_config,
- .qdev.props = (Property[]) {
- DEFINE_PROP_HEX32("bios-offset", PCIVGAState, vga.bios_offset, 0),
- DEFINE_PROP_HEX32("bios-size", PCIVGAState, vga.bios_size, 0),
- DEFINE_PROP_END_OF_LIST(),
- }
-};
-
-static void vga_register(void)
-{
- pci_qdev_register(&vga_info);
-}
-device_init(vga_register);
-
/********************************************************/
/* vga screen dump */
available */
static void vga_screen_dump(void *opaque, const char *filename)
{
- VGAState *s = opaque;
+ VGACommonState *s = opaque;
if (!screen_dump_dcl)
screen_dump_dcl = vga_screen_dump_init(s->ds);
projects / qemu.git / blobdiff