Sparc32: convert sparc32_dma to qdev

[qemu.git] / hw / sparc32_dma.c

diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index f272b24229808b4fc25c53afddfd84378ec335ea..a0678b5dbc2a70539260d3c3adb77880e95574a7 100644 (file)
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -21,9 +21,11 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
+
 #include "hw.h"
 #include "sparc32_dma.h"
 #include "sun4m.h"
+#include "sysbus.h"
 
 /* debug DMA */
 //#define DEBUG_DMA
@@ -60,6 +62,7 @@
 typedef struct DMAState DMAState;
 
 struct DMAState {
+    SysBusDevice busdev;
     uint32_t dmaregs[DMA_REGS];
     qemu_irq irq;
     void *iommu;
@@ -242,24 +245,56 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
 }
 
 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
-                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
+                       void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
 {
-    DMAState *s;
-    int dma_io_memory;
+    DeviceState *dev;
+    SysBusDevice *s;
+    DMAState *d;
+
+    dev = qdev_create(NULL, "sparc32_dma");
+    qdev_set_prop_ptr(dev, "iommu_opaque", iommu);
+    qdev_init(dev);
+    s = sysbus_from_qdev(dev);
+    sysbus_connect_irq(s, 0, parent_irq);
+    *dev_irq = qdev_get_gpio_in(dev, 0);
+    sysbus_mmio_map(s, 0, daddr);
+
+    d = FROM_SYSBUS(DMAState, s);
+    *reset = &d->dev_reset;
+
+    return d;
+}
 
-    s = qemu_mallocz(sizeof(DMAState));
+static void sparc32_dma_init1(SysBusDevice *dev)
+{
+    DMAState *s = FROM_SYSBUS(DMAState, dev);
+    int dma_io_memory;
 
-    s->irq = parent_irq;
-    s->iommu = iommu;
+    sysbus_init_irq(dev, &s->irq);
+    s->iommu = qdev_get_prop_ptr(&dev->qdev, "iommu_opaque");
 
     dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
-    cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
+    sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
 
-    register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
+    register_savevm("sparc32_dma", -1, 2, dma_save, dma_load, s);
     qemu_register_reset(dma_reset, s);
-    *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
 
-    *reset = &s->dev_reset;
+    qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
+}
 
-    return s;
+static SysBusDeviceInfo sparc32_dma_info = {
+    .init = sparc32_dma_init1,
+    .qdev.name  = "sparc32_dma",
+    .qdev.size  = sizeof(DMAState),
+    .qdev.props = (DevicePropList[]) {
+        {.name = "iommu_opaque", .type = PROP_TYPE_PTR},
+        {.name = NULL}
+    }
+};
+
+static void sparc32_dma_register_devices(void)
+{
+    sysbus_register_withprop(&sparc32_dma_info);
 }
+
+device_init(sparc32_dma_register_devices)