* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
+
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/host-utils.h"
#include "hw/hw.h"
-#include "hw/devices.h"
+#include "hw/irq.h"
+#include "hw/display/tc6393xb.h"
#include "hw/block/flash.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
blanked : 1;
};
-qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
-{
- return s->gpio_in;
-}
-
static void tc6393xb_gpio_set(void *opaque, int line, int level)
{
// TC6393xbState *s = opaque;
// FIXME: how does the chip reflect the GPIO input level change?
}
-void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
- qemu_irq handler)
-{
- if (line >= TC6393XB_GPIOS) {
- fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
- return;
- }
-
- s->handler[line] = handler;
-}
-
static void tc6393xb_gpio_handler_update(TC6393xbState *s)
{
uint32_t level, diff;
SCR_REG_B(DEBUG);
}
fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
- (uint32_t) addr, value & 0xff);
+ (uint32_t) addr, value & 0xff);
}
#undef SCR_REG_B
#undef SCR_REG_W
return;
}
fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
- (uint32_t) addr, value & 0xff);
+ (uint32_t) addr, value & 0xff);
}
static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
return;
}
fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
- (uint32_t) addr, value & 0xff);
+ (uint32_t) addr, value & 0xff);
}
#define BITS 8
return;
}
- dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
+ dpy_gfx_update_full(s->con);
}
static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
d += surface_stride(surface);
}
- dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
+ dpy_gfx_update_full(s->con);
}
static void tc6393xb_update_display(void *opaque)