PowerPC MMU and exception fixes:

[qemu.git] / target-ppc / exec.h

diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index e559d5c8c468459d9d143371605f5c9b97e93010..f561357044701b1baf4f51d663a790bb664e7efa 100644 (file)
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -1,7 +1,7 @@
 /*
  *  PowerPC emulation definitions for qemu.
 /*
  *  PowerPC emulation definitions for qemu.

- * 
- *  Copyright (c) 2003-2005 Jocelyn Mayer
+ *
+ *  Copyright (c) 2003-2007 Jocelyn Mayer

  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public


@@ -20,132 +20,109 @@
 #if !defined (__PPC_H__)
 #define __PPC_H__
 
 #if !defined (__PPC_H__)
 #define __PPC_H__
 

+#include "config.h"
+

 #include "dyngen-exec.h"
 
 #include "dyngen-exec.h"
 

+#include "cpu.h"
+#include "exec-all.h"
+
+/* For normal operations, precise emulation should not be needed */
+//#define USE_PRECISE_EMULATION 1
+#define USE_PRECISE_EMULATION 0
+

 register struct CPUPPCState *env asm(AREG0);
 register struct CPUPPCState *env asm(AREG0);

-register uint32_t T0 asm(AREG1);
-register uint32_t T1 asm(AREG2);
-register uint32_t T2 asm(AREG3);
+#if TARGET_LONG_BITS > HOST_LONG_BITS
+/* no registers can be used */
+#define T0 (env->t0)
+#define T1 (env->t1)
+#define T2 (env->t2)
+#else
+register unsigned long T0 asm(AREG1);
+register unsigned long T1 asm(AREG2);
+register unsigned long T2 asm(AREG3);
+#endif
+/* We may, sometime, need 64 bits registers on 32 bits target */
+#if TARGET_GPR_BITS > HOST_LONG_BITS
+/* no registers can be used */
+#define T0_64 (env->t0)
+#define T1_64 (env->t1)
+#define T2_64 (env->t2)
+#else
+#define T0_64 T0
+#define T1_64 T1
+#define T2_64 T2
+#endif
+/* Provision for Altivec */
+#define AVR0 (env->avr0)
+#define AVR1 (env->avr1)
+#define AVR2 (env->avr2)

 
 

-#define PARAM(n) ((uint32_t)PARAM##n)
-#define SPARAM(n) ((int32_t)PARAM##n)

 #define FT0 (env->ft0)
 #define FT1 (env->ft1)
 #define FT2 (env->ft2)
 
 #if defined (DEBUG_OP)
 #define FT0 (env->ft0)
 #define FT1 (env->ft1)
 #define FT2 (env->ft2)
 
 #if defined (DEBUG_OP)

-#define RETURN() __asm__ __volatile__("nop");
+# define RETURN() __asm__ __volatile__("nop" : : : "memory");

 #else
 #else

-#define RETURN() __asm__ __volatile__("");
+# define RETURN() __asm__ __volatile__("" : : : "memory");

 #endif
 
 #endif
 

-#include "cpu.h"
-#include "exec-all.h"
-
-static inline uint32_t rotl (uint32_t i, int n)
+static always_inline target_ulong rotl8 (target_ulong i, int n)

 {
 {

-    return ((i << n) | (i >> (32 - n)));
+    return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));

 }
 
 }
 

-/* XXX: move that to a generic header */
-#if !defined(CONFIG_USER_ONLY)
-
-#define ldul_user ldl_user
-#define ldul_kernel ldl_kernel
-
-#define ACCESS_TYPE 0
-#define MEMSUFFIX _kernel
-#define DATA_SIZE 1
-#include "softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "softmmu_header.h"
-#undef ACCESS_TYPE
-#undef MEMSUFFIX
-
-#define ACCESS_TYPE 1
-#define MEMSUFFIX _user
-#define DATA_SIZE 1
-#include "softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "softmmu_header.h"
-#undef ACCESS_TYPE
-#undef MEMSUFFIX
-
-/* these access are slower, they must be as rare as possible */
-#define ACCESS_TYPE 2
-#define MEMSUFFIX _data
-#define DATA_SIZE 1
-#include "softmmu_header.h"
-
-#define DATA_SIZE 2
-#include "softmmu_header.h"
-
-#define DATA_SIZE 4
-#include "softmmu_header.h"
-
-#define DATA_SIZE 8
-#include "softmmu_header.h"
-#undef ACCESS_TYPE
-#undef MEMSUFFIX
+static always_inline target_ulong rotl16 (target_ulong i, int n)
+{
+    return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
+}

 
 

-#define ldub(p) ldub_data(p)
-#define ldsb(p) ldsb_data(p)
-#define lduw(p) lduw_data(p)
-#define ldsw(p) ldsw_data(p)
-#define ldl(p) ldl_data(p)
-#define ldq(p) ldq_data(p)
+static always_inline target_ulong rotl32 (target_ulong i, int n)
+{
+    return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
+}

 
 

-#define stb(p, v) stb_data(p, v)
-#define stw(p, v) stw_data(p, v)
-#define stl(p, v) stl_data(p, v)
-#define stq(p, v) stq_data(p, v)
+#if defined(TARGET_PPC64)
+static always_inline target_ulong rotl64 (target_ulong i, int n)
+{
+    return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
+}
+#endif

 
 

+#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"

 #endif /* !defined(CONFIG_USER_ONLY) */
 
 void do_raise_exception_err (uint32_t exception, int error_code);
 void do_raise_exception (uint32_t exception);
 
 #endif /* !defined(CONFIG_USER_ONLY) */
 
 void do_raise_exception_err (uint32_t exception, int error_code);
 void do_raise_exception (uint32_t exception);
 

-void do_sraw(void);
-
-void do_fctiw (void);
-void do_fctiwz (void);
-void do_fnmadd (void);
-void do_fnmsub (void);
-void do_fsqrt (void);
-void do_fres (void);
-void do_frsqrte (void);
-void do_fsel (void);
-void do_fcmpu (void);
-void do_fcmpo (void);
-
-void do_check_reservation (void);
-void do_icbi (void);
-void do_tlbia (void);
-void do_tlbie (void);
-
-static inline void env_to_regs(void)
+int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
+                          int rw, int access_type);
+
+void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
+                       target_ulong pte0, target_ulong pte1);
+
+static always_inline void env_to_regs (void)

 {
 }
 
 {
 }
 

-static inline void regs_to_env(void)
+static always_inline void regs_to_env (void)

 {
 }
 
 {
 }
 

-int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
-                              int is_user, int is_softmmu);
+int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+                              int mmu_idx, int is_softmmu);
+
+static always_inline int cpu_halted (CPUState *env)
+{
+    if (!env->halted)
+        return 0;
+    if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
+        env->halted = 0;
+        return 0;
+    }
+    return EXCP_HALTED;
+}

 
 #endif /* !defined (__PPC_H__) */
 
 #endif /* !defined (__PPC_H__) */