* GNU GPL, version 2 or (at your option) any later version.
*/
-#include "memory.h"
-#include "exec-memory.h"
-#include "ioport.h"
-#include "bitops.h"
-#include "kvm.h"
+#include "exec/memory.h"
+#include "exec/address-spaces.h"
+#include "exec/ioport.h"
+#include "qemu/bitops.h"
+#include "sysemu/kvm.h"
#include <assert.h>
-#include "memory-internal.h"
+#include "exec/memory-internal.h"
-unsigned memory_region_transaction_depth = 0;
+static unsigned memory_region_transaction_depth;
+static bool memory_region_update_pending;
static bool global_dirty_log = false;
static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
assert(memory_region_transaction_depth);
--memory_region_transaction_depth;
- if (!memory_region_transaction_depth) {
+ if (!memory_region_transaction_depth && memory_region_update_pending) {
+ memory_region_update_pending = false;
MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
}
if (!mr->ops->read) {
- return mr->ops->old_mmio.read[bitops_ffsl(size)](mr->opaque, addr);
+ return mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
}
/* FIXME: support unaligned access */
adjust_endianness(mr, &data, size);
if (!mr->ops->write) {
- mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data);
+ mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, data);
return;
}
memory_region_transaction_begin();
mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
+ memory_region_update_pending |= mr->enabled;
memory_region_transaction_commit();
}
return cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size, -1);
}
+bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size, unsigned client)
+{
+ bool ret;
+ assert(mr->terminates);
+ ret = cpu_physical_memory_get_dirty(mr->ram_addr + addr, size,
+ 1 << client);
+ if (ret) {
+ cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
+ mr->ram_addr + addr + size,
+ 1 << client);
+ }
+ return ret;
+}
+
+
void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
{
AddressSpace *as;
if (mr->readonly != readonly) {
memory_region_transaction_begin();
mr->readonly = readonly;
+ memory_region_update_pending |= mr->enabled;
memory_region_transaction_commit();
}
}
if (mr->readable != readable) {
memory_region_transaction_begin();
mr->readable = readable;
+ memory_region_update_pending |= mr->enabled;
memory_region_transaction_commit();
}
}
memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
mr->ioeventfds[i] = mrfd;
+ memory_region_update_pending |= mr->enabled;
memory_region_transaction_commit();
}
--mr->ioeventfd_nb;
mr->ioeventfds = g_realloc(mr->ioeventfds,
sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
+ memory_region_update_pending |= mr->enabled;
memory_region_transaction_commit();
}
if (subregion->may_overlap || other->may_overlap) {
continue;
}
- if (int128_gt(int128_make64(offset),
+ if (int128_ge(int128_make64(offset),
int128_add(int128_make64(other->addr), other->size))
|| int128_le(int128_add(int128_make64(offset), subregion->size),
int128_make64(other->addr))) {
}
QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
done:
+ memory_region_update_pending |= mr->enabled && subregion->enabled;
memory_region_transaction_commit();
}
assert(subregion->parent == mr);
subregion->parent = NULL;
QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
+ memory_region_update_pending |= mr->enabled && subregion->enabled;
memory_region_transaction_commit();
}
}
memory_region_transaction_begin();
mr->enabled = enabled;
+ memory_region_update_pending = true;
memory_region_transaction_commit();
}
memory_region_transaction_begin();
mr->alias_offset = offset;
+ memory_region_update_pending |= mr->enabled;
memory_region_transaction_commit();
}
const MemoryRegion *submr;
unsigned int i;
- if (!mr) {
+ if (!mr || !mr->enabled) {
return;
}