* Copyright (c) 2005-2006 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
#include "sysbus.h"
-#include "qemu-timer.h"
+#include "qemu/timer.h"
+#include "qemu-common.h"
+#include "qdev.h"
+#include "ptimer.h"
/* Common timer implementation. */
}
}
-static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t arm_timer_read(void *opaque, hwaddr offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
return 0;
return s->int_level;
default:
- hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset %x\n", __func__, (int)offset);
return 0;
}
}
ptimer_set_limit(s->timer, limit, reload);
}
-static void arm_timer_write(void *opaque, target_phys_addr_t offset,
+static void arm_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
arm_timer_recalibrate(s, 0);
break;
default:
- hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset %x\n", __func__, (int)offset);
}
arm_timer_update(s);
}
arm_timer_update(s);
}
-static void arm_timer_save(QEMUFile *f, void *opaque)
-{
- arm_timer_state *s = (arm_timer_state *)opaque;
- qemu_put_be32(f, s->control);
- qemu_put_be32(f, s->limit);
- qemu_put_be32(f, s->int_level);
- qemu_put_ptimer(f, s->timer);
-}
-
-static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
-{
- arm_timer_state *s = (arm_timer_state *)opaque;
-
- if (version_id != 1)
- return -EINVAL;
-
- s->control = qemu_get_be32(f);
- s->limit = qemu_get_be32(f);
- s->int_level = qemu_get_be32(f);
- qemu_get_ptimer(f, s->timer);
- return 0;
-}
+static const VMStateDescription vmstate_arm_timer = {
+ .name = "arm_timer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(control, arm_timer_state),
+ VMSTATE_UINT32(limit, arm_timer_state),
+ VMSTATE_INT32(int_level, arm_timer_state),
+ VMSTATE_PTIMER(timer, arm_timer_state),
+ VMSTATE_END_OF_LIST()
+ }
+};
static arm_timer_state *arm_timer_init(uint32_t freq)
{
arm_timer_state *s;
QEMUBH *bh;
- s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
+ s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
s->freq = freq;
s->control = TIMER_CTRL_IE;
bh = qemu_bh_new(arm_timer_tick, s);
s->timer = ptimer_init(bh);
- register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
+ vmstate_register(NULL, -1, &vmstate_arm_timer, s);
return s;
}
/* ARM PrimeCell SP804 dual timer module.
- Docs for this device don't seem to be publicly available. This
- implementation is based on guesswork, the linux kernel sources and the
- Integrator/CP timer modules. */
+ * Docs at
+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
+*/
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[2];
+ uint32_t freq0, freq1;
int level[2];
qemu_irq irq;
} sp804_state;
+static const uint8_t sp804_ids[] = {
+ /* Timer ID */
+ 0x04, 0x18, 0x14, 0,
+ /* PrimeCell ID */
+ 0xd, 0xf0, 0x05, 0xb1
+};
+
/* Merge the IRQs from the two component devices. */
static void sp804_set_irq(void *opaque, int irq, int level)
{
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
+static uint64_t sp804_read(void *opaque, hwaddr offset,
+ unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
- /* ??? Don't know the PrimeCell ID for this device. */
if (offset < 0x20) {
return arm_timer_read(s->timer[0], offset);
- } else {
+ }
+ if (offset < 0x40) {
return arm_timer_read(s->timer[1], offset - 0x20);
}
+
+ /* TimerPeriphID */
+ if (offset >= 0xfe0 && offset <= 0xffc) {
+ return sp804_ids[(offset - 0xfe0) >> 2];
+ }
+
+ switch (offset) {
+ /* Integration Test control registers, which we won't support */
+ case 0xf00: /* TimerITCR */
+ case 0xf04: /* TimerITOP (strictly write only but..) */
+ qemu_log_mask(LOG_UNIMP,
+ "%s: integration test registers unimplemented\n",
+ __func__);
+ return 0;
+ }
+
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset %x\n", __func__, (int)offset);
+ return 0;
}
-static void sp804_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+static void sp804_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
if (offset < 0x20) {
arm_timer_write(s->timer[0], offset, value);
- } else {
+ return;
+ }
+
+ if (offset < 0x40) {
arm_timer_write(s->timer[1], offset - 0x20, value);
+ return;
}
+
+ /* Technically we could be writing to the Test Registers, but not likely */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
+ __func__, (int)offset);
}
-static CPUReadMemoryFunc * const sp804_readfn[] = {
- sp804_read,
- sp804_read,
- sp804_read
+static const MemoryRegionOps sp804_ops = {
+ .read = sp804_read,
+ .write = sp804_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const sp804_writefn[] = {
- sp804_write,
- sp804_write,
- sp804_write
+static const VMStateDescription vmstate_sp804 = {
+ .name = "sp804",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_INT32_ARRAY(level, sp804_state, 2),
+ VMSTATE_END_OF_LIST()
+ }
};
-static void sp804_save(QEMUFile *f, void *opaque)
-{
- sp804_state *s = (sp804_state *)opaque;
- qemu_put_be32(f, s->level[0]);
- qemu_put_be32(f, s->level[1]);
-}
-
-static int sp804_load(QEMUFile *f, void *opaque, int version_id)
-{
- sp804_state *s = (sp804_state *)opaque;
-
- if (version_id != 1)
- return -EINVAL;
-
- s->level[0] = qemu_get_be32(f);
- s->level[1] = qemu_get_be32(f);
- return 0;
-}
-
static int sp804_init(SysBusDevice *dev)
{
- int iomemtype;
sp804_state *s = FROM_SYSBUS(sp804_state, dev);
qemu_irq *qi;
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
sysbus_init_irq(dev, &s->irq);
- /* ??? The timers are actually configurable between 32kHz and 1MHz, but
- we don't implement that. */
- s->timer[0] = arm_timer_init(1000000);
- s->timer[1] = arm_timer_init(1000000);
+ s->timer[0] = arm_timer_init(s->freq0);
+ s->timer[1] = arm_timer_init(s->freq1);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
- iomemtype = cpu_register_io_memory(sp804_readfn,
- sp804_writefn, s);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
- register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
+ memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
+ vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
-
/* Integrator/CP timer module. */
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[3];
} icp_pit_state;
-static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
+static uint64_t icp_pit_read(void *opaque, hwaddr offset,
+ unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
/* ??? Don't know the PrimeCell ID for this device. */
n = offset >> 8;
- if (n > 3) {
- hw_error("sp804_read: Bad timer %d\n", n);
+ if (n > 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
}
return arm_timer_read(s->timer[n], offset & 0xff);
}
-static void icp_pit_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+static void icp_pit_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
n = offset >> 8;
- if (n > 3) {
- hw_error("sp804_write: Bad timer %d\n", n);
+ if (n > 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
}
arm_timer_write(s->timer[n], offset & 0xff, value);
}
-
-static CPUReadMemoryFunc * const icp_pit_readfn[] = {
- icp_pit_read,
- icp_pit_read,
- icp_pit_read
-};
-
-static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
- icp_pit_write,
- icp_pit_write,
- icp_pit_write
+static const MemoryRegionOps icp_pit_ops = {
+ .read = icp_pit_read,
+ .write = icp_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pit_init(SysBusDevice *dev)
{
- int iomemtype;
icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
/* Timer 0 runs at the system clock speed (40MHz). */
sysbus_init_irq(dev, &s->timer[1]->irq);
sysbus_init_irq(dev, &s->timer[2]->irq);
- iomemtype = cpu_register_io_memory(icp_pit_readfn,
- icp_pit_writefn, s);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
/* This device has no state to save/restore. The component timers will
save themselves. */
return 0;
}
-static void arm_timer_register_devices(void)
+static void icp_pit_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = icp_pit_init;
+}
+
+static const TypeInfo icp_pit_info = {
+ .name = "integrator_pit",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(icp_pit_state),
+ .class_init = icp_pit_class_init,
+};
+
+static Property sp804_properties[] = {
+ DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
+ DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sp804_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+ DeviceClass *k = DEVICE_CLASS(klass);
+
+ sdc->init = sp804_init;
+ k->props = sp804_properties;
+}
+
+static const TypeInfo sp804_info = {
+ .name = "sp804",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(sp804_state),
+ .class_init = sp804_class_init,
+};
+
+static void arm_timer_register_types(void)
{
- sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
- sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
+ type_register_static(&icp_pit_info);
+ type_register_static(&sp804_info);
}
-device_init(arm_timer_register_devices)
+type_init(arm_timer_register_types)
projects / qemu.git / blobdiff