janitor: do not rely on indirect inclusions of or from qemu-char.h

[qemu.git] / hw / etraxfs_pic.c

diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
index f32b3021c4ac3e50a2cce8b657b07f3123cb873a..62a62a36af0a415c1dbc9b99d8fbb3d522ec20db 100644 (file)
--- a/hw/etraxfs_pic.c
+++ b/hw/etraxfs_pic.c
@@ -22,185 +22,159 @@
  * THE SOFTWARE.
  */
 
  * THE SOFTWARE.
  */
 

-#include <stdio.h>
+#include "sysbus.h"

 #include "hw.h"
 #include "hw.h"

-#include "pc.h"
-#include "etraxfs.h"
+//#include "pc.h"
+//#include "etraxfs.h"

 
 #define D(x)
 
 
 #define D(x)
 

-struct fs_pic_state_t
+#define R_RW_MASK   0
+#define R_R_VECT    1
+#define R_R_MASKED_VECT 2
+#define R_R_NMI     3
+#define R_R_GURU    4
+#define R_MAX       5
+
+struct etrax_pic

 {
 {

-       CPUState *env;
-
-       uint32_t rw_mask;
-       /* Active interrupt lines.  */
-       uint32_t r_vect;
-       /* Active lines, gated through the mask.  */
-       uint32_t r_masked_vect;
-       uint32_t r_nmi;
-       uint32_t r_guru;
+    SysBusDevice busdev;
+    MemoryRegion mmio;
+    void *interrupt_vector;
+    qemu_irq parent_irq;
+    qemu_irq parent_nmi;
+    uint32_t regs[R_MAX];

 };
 
 };
 

-static void pic_update(struct fs_pic_state_t *fs)
-{      
-       CPUState *env = fs->env;
-       int i;
-       uint32_t vector = 0;
-
-       fs->r_masked_vect = fs->r_vect & fs->rw_mask;
-
-       /* The ETRAX interrupt controller signals interrupts to teh core
-          through an interrupt request wire and an irq vector bus. If 
-          multiple interrupts are simultaneously active it chooses vector 
-          0x30 and lets the sw choose the priorities.  */
-       if (fs->r_masked_vect) {
-               uint32_t mv = fs->r_masked_vect;
-               for (i = 0; i < 31; i++) {
-                       if (mv & 1) {
-                               vector = 0x31 + i;
-                               /* Check for multiple interrupts.  */
-                               if (mv > 1)
-                                       vector = 0x30;
-                               break;
-                       }
-                       mv >>= 1;
-               }
-               if (vector) {
-                       env->interrupt_vector = vector;
-                       D(printf("%s vector=%x\n", __func__, vector));
-                       cpu_interrupt(env, CPU_INTERRUPT_HARD);
-               }
-       } else {
-               env->interrupt_vector = 0;
-               cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
-               D(printf("%s reset irqs\n", __func__));
-       }
+static void pic_update(struct etrax_pic *fs)
+{   
+    uint32_t vector = 0;
+    int i;
+
+    fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
+
+    /* The ETRAX interrupt controller signals interrupts to the core
+       through an interrupt request wire and an irq vector bus. If 
+       multiple interrupts are simultaneously active it chooses vector 
+       0x30 and lets the sw choose the priorities.  */
+    if (fs->regs[R_R_MASKED_VECT]) {
+        uint32_t mv = fs->regs[R_R_MASKED_VECT];
+        for (i = 0; i < 31; i++) {
+            if (mv & 1) {
+                vector = 0x31 + i;
+                /* Check for multiple interrupts.  */
+                if (mv > 1)
+                    vector = 0x30;
+                break;
+            }
+            mv >>= 1;
+        }
+    }
+
+    if (fs->interrupt_vector) {
+        /* hack alert: ptr property */
+        *(uint32_t*)(fs->interrupt_vector) = vector;
+    }
+    qemu_set_irq(fs->parent_irq, !!vector);

 }
 
 }
 

-static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+pic_read(void *opaque, hwaddr addr, unsigned int size)

 {
 {

-       struct fs_pic_state_t *fs = opaque;
-       uint32_t rval;
-
-       switch (addr)
-       {
-               case 0x0: 
-                       rval = fs->rw_mask;
-                       break;
-               case 0x4: 
-                       rval = fs->r_vect;
-                       break;
-               case 0x8: 
-                       rval = fs->r_masked_vect;
-                       break;
-               case 0xc: 
-                       rval = fs->r_nmi;
-                       break;
-               case 0x10: 
-                       rval = fs->r_guru;
-                       break;
-               default:
-                       cpu_abort(fs->env, "invalid PIC register.\n");
-                       break;
-
-       }
-       D(printf("%s %x=%x\n", __func__, addr, rval));
-       return rval;
+    struct etrax_pic *fs = opaque;
+    uint32_t rval;
+
+    rval = fs->regs[addr >> 2];
+    D(printf("%s %x=%x\n", __func__, addr, rval));
+    return rval;

 }
 
 }
 

-static void
-pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void pic_write(void *opaque, hwaddr addr,
+                      uint64_t value, unsigned int size)

 {
 {

-       struct fs_pic_state_t *fs = opaque;
-       D(printf("%s addr=%x val=%x\n", __func__, addr, value));
-       switch (addr) 
-       {
-               case 0x0: 
-                       fs->rw_mask = value;
-                       pic_update(fs);
-                       break;
-               default:
-                       cpu_abort(fs->env, "invalid PIC register.\n");
-                       break;
-       }
+    struct etrax_pic *fs = opaque;
+    D(printf("%s addr=%x val=%x\n", __func__, addr, value));
+
+    if (addr == R_RW_MASK) {
+        fs->regs[R_RW_MASK] = value;
+        pic_update(fs);
+    }

 }
 
 }
 

-static CPUReadMemoryFunc *pic_read[] = {
-       NULL, NULL,
-       &pic_readl,
+static const MemoryRegionOps pic_ops = {
+    .read = pic_read,
+    .write = pic_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4
+    }

 };
 
 };
 

-static CPUWriteMemoryFunc *pic_write[] = {
-       NULL, NULL,
-       &pic_writel,
-};
+static void nmi_handler(void *opaque, int irq, int level)
+{   
+    struct etrax_pic *fs = (void *)opaque;
+    uint32_t mask;

 
 

-void pic_info(Monitor *mon)
-{
-}
+    mask = 1 << irq;
+    if (level)
+        fs->regs[R_R_NMI] |= mask;
+    else
+        fs->regs[R_R_NMI] &= ~mask;

 
 

-void irq_info(Monitor *mon)
-{
+    qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);

 }
 
 static void irq_handler(void *opaque, int irq, int level)
 }
 
 static void irq_handler(void *opaque, int irq, int level)

-{      
-       struct fs_pic_state_t *fs = (void *)opaque;
+{   
+    struct etrax_pic *fs = (void *)opaque;

 
 

-       D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n", 
-                __func__, irq, level,
-                fs->rw_mask, fs->r_vect, fs->r_masked_vect));
+    if (irq >= 30)
+        return nmi_handler(opaque, irq, level);

 
 

-       irq -= 1;
-       fs->r_vect &= ~(1 << irq);
-       fs->r_vect |= (!!level << irq);
-
-       pic_update(fs);
+    irq -= 1;
+    fs->regs[R_R_VECT] &= ~(1 << irq);
+    fs->regs[R_R_VECT] |= (!!level << irq);
+    pic_update(fs);

 }
 
 }
 

-static void nmi_handler(void *opaque, int irq, int level)
-{      
-       struct fs_pic_state_t *fs = (void *)opaque;
-       CPUState *env = fs->env;
-       uint32_t mask;
-
-       mask = 1 << irq;
-       if (level)
-               fs->r_nmi |= mask;
-       else
-               fs->r_nmi &= ~mask;
-
-       if (fs->r_nmi)
-               cpu_interrupt(env, CPU_INTERRUPT_NMI);
-       else
-               cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
-}
+static int etraxfs_pic_init(SysBusDevice *dev)
+{
+    struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev);

 
 

-static void guru_handler(void *opaque, int irq, int level)
-{      
-       struct fs_pic_state_t *fs = (void *)opaque;
-       CPUState *env = fs->env;
-       cpu_abort(env, "%s unsupported exception\n", __func__);
+    qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
+    sysbus_init_irq(dev, &s->parent_irq);
+    sysbus_init_irq(dev, &s->parent_nmi);

 
 

+    memory_region_init_io(&s->mmio, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
+    sysbus_init_mmio(dev, &s->mmio);
+    return 0;

 }
 
 }
 

-struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
-{
-       struct fs_pic_state_t *fs = NULL;
-       struct etraxfs_pic *pic = NULL;
-       int intr_vect_regs;
+static Property etraxfs_pic_properties[] = {
+    DEFINE_PROP_PTR("interrupt_vector", struct etrax_pic, interrupt_vector),
+    DEFINE_PROP_END_OF_LIST(),
+};

 
 

-       pic = qemu_mallocz(sizeof *pic);
-       pic->internal = fs = qemu_mallocz(sizeof *fs);
+static void etraxfs_pic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

 
 

-       fs->env = env;
-       pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
-       pic->nmi = qemu_allocate_irqs(nmi_handler, fs, 2);
-       pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
+    k->init = etraxfs_pic_init;
+    dc->props = etraxfs_pic_properties;
+}

 
 

-       intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
-       cpu_register_physical_memory(base, 0x14, intr_vect_regs);
+static TypeInfo etraxfs_pic_info = {
+    .name          = "etraxfs,pic",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(struct etrax_pic),
+    .class_init    = etraxfs_pic_class_init,
+};

 
 

-       return pic;
+static void etraxfs_pic_register_types(void)
+{
+    type_register_static(&etraxfs_pic_info);

 }
 }

+
+type_init(etraxfs_pic_register_types)