ac97: Use PCI DMA stub functions

[qemu.git] / hw / ide / mmio.c

diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
index 99ddf9d4d951e92874eb99092bb8f4743c438976..2ec21b01632114afcc071695c74895b9fc95b085 100644 (file)
--- a/hw/ide/mmio.c
+++ b/hw/ide/mmio.c
@@ -24,8 +24,6 @@
  */
 #include <hw/hw.h>
 #include "block.h"
-#include "block_int.h"
-#include "sysemu.h"
 #include "dma.h"
 
 #include <hw/ide/internal.h>
@@ -37,31 +35,36 @@
  */
 
 typedef struct {
-    IDEBus *bus;
+    IDEBus bus;
     int shift;
 } MMIOState;
 
+static void mmio_ide_reset(void *opaque)
+{
+    MMIOState *s = opaque;
+
+    ide_bus_reset(&s->bus);
+}
+
 static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
 {
-    MMIOState *s = (MMIOState*)opaque;
-    IDEBus *bus = s->bus;
+    MMIOState *s = opaque;
     addr >>= s->shift;
     if (addr & 7)
-        return ide_ioport_read(bus, addr);
+        return ide_ioport_read(&s->bus, addr);
     else
-        return ide_data_readw(bus, 0);
+        return ide_data_readw(&s->bus, 0);
 }
 
 static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
        uint32_t val)
 {
-    MMIOState *s = (MMIOState*)opaque;
-    IDEBus *bus = s->bus;
+    MMIOState *s = opaque;
     addr >>= s->shift;
     if (addr & 7)
-        ide_ioport_write(bus, addr, val);
+        ide_ioport_write(&s->bus, addr, val);
     else
-        ide_data_writew(bus, 0, val);
+        ide_data_writew(&s->bus, 0, val);
 }
 
 static CPUReadMemoryFunc * const mmio_ide_reads[] = {
@@ -78,17 +81,15 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
 
 static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
 {
-    MMIOState *s= (MMIOState*)opaque;
-    IDEBus *bus = s->bus;
-    return ide_status_read(bus, 0);
+    MMIOState *s= opaque;
+    return ide_status_read(&s->bus, 0);
 }
 
 static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
        uint32_t val)
 {
-    MMIOState *s = (MMIOState*)opaque;
-    IDEBus *bus = s->bus;
-    ide_cmd_write(bus, 0, val);
+    MMIOState *s = opaque;
+    ide_cmd_write(&s->bus, 0, val);
 }
 
 static CPUReadMemoryFunc * const mmio_ide_status[] = {
@@ -103,42 +104,36 @@ static CPUWriteMemoryFunc * const mmio_ide_cmd[] = {
     mmio_ide_cmd_write,
 };
 
-static void mmio_ide_save(QEMUFile* f, void *opaque)
-{
-    MMIOState *s = opaque;
-
-    idebus_save(f, s->bus);
-    ide_save(f, &s->bus->ifs[0]);
-    ide_save(f, &s->bus->ifs[1]);
-}
-
-static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id)
-{
-    MMIOState *s = opaque;
-
-    idebus_load(f, s->bus, version_id);
-    ide_load(f, &s->bus->ifs[0], version_id);
-    ide_load(f, &s->bus->ifs[1], version_id);
-    return 0;
-}
+static const VMStateDescription vmstate_ide_mmio = {
+    .name = "mmio-ide",
+    .version_id = 3,
+    .minimum_version_id = 0,
+    .minimum_version_id_old = 0,
+    .fields      = (VMStateField []) {
+        VMSTATE_IDE_BUS(bus, MMIOState),
+        VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
+        VMSTATE_END_OF_LIST()
+    }
+};
 
 void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
                     qemu_irq irq, int shift,
-                    BlockDriverState *hd0, BlockDriverState *hd1)
+                    DriveInfo *hd0, DriveInfo *hd1)
 {
-    MMIOState *s = qemu_mallocz(sizeof(MMIOState));
-    IDEBus *bus = qemu_mallocz(sizeof(*bus));
+    MMIOState *s = g_malloc0(sizeof(MMIOState));
     int mem1, mem2;
 
-    ide_init2(bus, hd0, hd1, irq);
+    ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq);
 
-    s->bus = bus;
     s->shift = shift;
 
-    mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
-    mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
+    mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s,
+                                  DEVICE_NATIVE_ENDIAN);
+    mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s,
+                                  DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(membase, 16 << shift, mem1);
     cpu_register_physical_memory(membase2, 2 << shift, mem2);
-    register_savevm("mmio-ide", 0, 3, mmio_ide_save, mmio_ide_load, s);
+    vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
+    qemu_register_reset(mmio_ide_reset, s);
 }