#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
+#include <hw/isa.h>
#include "block.h"
#include "block_int.h"
#include "sysemu.h"
#include "dma.h"
-#include <hw/ide/internal.h>
+#include <hw/ide/pci.h>
-/***********************************************************/
-/* PCI IDE definitions */
-
-/* CMD646 specific */
-#define MRDMODE 0x71
-#define MRDMODE_INTR_CH0 0x04
-#define MRDMODE_INTR_CH1 0x08
-#define MRDMODE_BLK_CH0 0x10
-#define MRDMODE_BLK_CH1 0x20
-#define UDIDETCR0 0x73
-#define UDIDETCR1 0x7B
-
-#define IDE_TYPE_PIIX3 0
-#define IDE_TYPE_CMD646 1
-#define IDE_TYPE_PIIX4 2
-
-typedef struct PCIIDEState {
- PCIDevice dev;
- IDEBus bus[2];
- BMDMAState bmdma[2];
- int type; /* see IDE_TYPE_xxx */
-} PCIIDEState;
-
-static void cmd646_update_irq(PCIIDEState *d);
-
-static void ide_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
-{
- PCIIDEState *d = (PCIIDEState *)pci_dev;
- IDEBus *bus;
-
- if (region_num <= 3) {
- bus = &d->bus[(region_num >> 1)];
- if (region_num & 1) {
- register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
- register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
- } else {
- register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
- register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
-
- /* data ports */
- register_ioport_write(addr, 2, 2, ide_data_writew, bus);
- register_ioport_read(addr, 2, 2, ide_data_readw, bus);
- register_ioport_write(addr, 4, 4, ide_data_writel, bus);
- register_ioport_read(addr, 4, 4, ide_data_readl, bus);
- }
- }
-}
-
-static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
#ifdef DEBUG_IDE
printf("%s: 0x%08x\n", __func__, val);
#endif
if (!(val & BM_CMD_START)) {
- /* XXX: do it better */
- ide_dma_cancel(bm);
+ /*
+ * We can't cancel Scatter Gather DMA in the middle of the
+ * operation or a partial (not full) DMA transfer would reach
+ * the storage so we wait for completion instead (we beahve
+ * like if the DMA was completed by the time the guest trying
+ * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
+ * set).
+ *
+ * In the future we'll be able to safely cancel the I/O if the
+ * whole DMA operation will be submitted to disk with a single
+ * aio operation with preadv/pwritev.
+ */
+ if (bm->aiocb) {
+ qemu_aio_flush();
+#ifdef DEBUG_IDE
+ if (bm->aiocb)
+ printf("ide_dma_cancel: aiocb still pending");
+ if (bm->status & BM_STATUS_DMAING)
+ printf("ide_dma_cancel: BM_STATUS_DMAING still pending");
+#endif
+ }
bm->cmd = val & 0x09;
} else {
if (!(bm->status & BM_STATUS_DMAING)) {
}
}
-static uint32_t bmdma_readb(void *opaque, uint32_t addr)
-{
- BMDMAState *bm = opaque;
- PCIIDEState *pci_dev;
- uint32_t val;
-
- switch(addr & 3) {
- case 0:
- val = bm->cmd;
- break;
- case 1:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- val = pci_dev->dev.config[MRDMODE];
- } else {
- val = 0xff;
- }
- break;
- case 2:
- val = bm->status;
- break;
- case 3:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- if (bm == &pci_dev->bmdma[0])
- val = pci_dev->dev.config[UDIDETCR0];
- else
- val = pci_dev->dev.config[UDIDETCR1];
- } else {
- val = 0xff;
- }
- break;
- default:
- val = 0xff;
- break;
- }
-#ifdef DEBUG_IDE
- printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
-#endif
- return val;
-}
-
-static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
- BMDMAState *bm = opaque;
- PCIIDEState *pci_dev;
-#ifdef DEBUG_IDE
- printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
-#endif
- switch(addr & 3) {
- case 1:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- pci_dev->dev.config[MRDMODE] =
- (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
- cmd646_update_irq(pci_dev);
- }
- break;
- case 2:
- bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
- break;
- case 3:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- if (bm == &pci_dev->bmdma[0])
- pci_dev->dev.config[UDIDETCR0] = val;
- else
- pci_dev->dev.config[UDIDETCR1] = val;
- }
- break;
- }
-}
-
-static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
+uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
{
BMDMAState *bm = opaque;
uint32_t val;
return val;
}
-static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
int shift = (addr & 3) * 8;
bm->cur_addr = bm->addr;
}
-static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
+uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
{
BMDMAState *bm = opaque;
uint32_t val;
return val;
}
-static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
int shift = (addr & 3) * 8;
bm->cur_addr = bm->addr;
}
-static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
+uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
{
BMDMAState *bm = opaque;
uint32_t val;
return val;
}
-static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
#ifdef DEBUG_IDE
bm->cur_addr = bm->addr;
}
-static void bmdma_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+static bool ide_bmdma_current_needed(void *opaque)
{
- PCIIDEState *d = (PCIIDEState *)pci_dev;
- int i;
-
- for(i = 0;i < 2; i++) {
- BMDMAState *bm = &d->bmdma[i];
- d->bus[i].bmdma = bm;
- bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
- bm->bus = d->bus+i;
- qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
-
- register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
-
- register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
- register_ioport_read(addr, 4, 1, bmdma_readb, bm);
+ BMDMAState *bm = opaque;
- register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
- register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
- register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
- register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
- register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
- register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
- addr += 8;
- }
+ return (bm->cur_prd_len != 0);
}
-static void pci_ide_save(QEMUFile* f, void *opaque)
-{
- PCIIDEState *d = opaque;
- int i;
-
- pci_device_save(&d->dev, f);
-
- for(i = 0; i < 2; i++) {
- BMDMAState *bm = &d->bmdma[i];
- uint8_t ifidx;
- qemu_put_8s(f, &bm->cmd);
- qemu_put_8s(f, &bm->status);
- qemu_put_be32s(f, &bm->addr);
- qemu_put_sbe64s(f, &bm->sector_num);
- qemu_put_be32s(f, &bm->nsector);
- ifidx = bm->unit + 2*i;
- qemu_put_8s(f, &ifidx);
- /* XXX: if a transfer is pending, we do not save it yet */
+static const VMStateDescription vmstate_bmdma_current = {
+ .name = "ide bmdma_current",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(cur_addr, BMDMAState),
+ VMSTATE_UINT32(cur_prd_last, BMDMAState),
+ VMSTATE_UINT32(cur_prd_addr, BMDMAState),
+ VMSTATE_UINT32(cur_prd_len, BMDMAState),
+ VMSTATE_END_OF_LIST()
}
-
- /* per IDE interface data */
- for(i = 0; i < 2; i++) {
- idebus_save(f, &d->bus[i]);
- }
-
- /* per IDE drive data */
- for(i = 0; i < 2; i++) {
- ide_save(f, &d->bus[i].ifs[0]);
- ide_save(f, &d->bus[i].ifs[1]);
+};
+
+
+static const VMStateDescription vmstate_bmdma = {
+ .name = "ide bmdma",
+ .version_id = 3,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(cmd, BMDMAState),
+ VMSTATE_UINT8(status, BMDMAState),
+ VMSTATE_UINT32(addr, BMDMAState),
+ VMSTATE_INT64(sector_num, BMDMAState),
+ VMSTATE_UINT32(nsector, BMDMAState),
+ VMSTATE_UINT8(unit, BMDMAState),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (VMStateSubsection []) {
+ {
+ .vmsd = &vmstate_bmdma_current,
+ .needed = ide_bmdma_current_needed,
+ }, {
+ /* empty */
+ }
}
-}
+};
-static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
+static int ide_pci_post_load(void *opaque, int version_id)
{
PCIIDEState *d = opaque;
- int ret, i;
-
- if (version_id != 2 && version_id != 3)
- return -EINVAL;
- ret = pci_device_load(&d->dev, f);
- if (ret < 0)
- return ret;
-
- for(i = 0; i < 2; i++) {
- BMDMAState *bm = &d->bmdma[i];
- uint8_t ifidx;
- qemu_get_8s(f, &bm->cmd);
- qemu_get_8s(f, &bm->status);
- qemu_get_be32s(f, &bm->addr);
- qemu_get_sbe64s(f, &bm->sector_num);
- qemu_get_be32s(f, &bm->nsector);
- qemu_get_8s(f, &ifidx);
- bm->unit = ifidx & 1;
- /* XXX: if a transfer is pending, we do not save it yet */
- }
-
- /* per IDE interface data */
- for(i = 0; i < 2; i++) {
- idebus_load(f, &d->bus[i], version_id);
- }
+ int i;
- /* per IDE drive data */
for(i = 0; i < 2; i++) {
- ide_load(f, &d->bus[i].ifs[0], version_id);
- ide_load(f, &d->bus[i].ifs[1], version_id);
+ /* current versions always store 0/1, but older version
+ stored bigger values. We only need last bit */
+ d->bmdma[i].unit &= 1;
}
return 0;
}
-/* XXX: call it also when the MRDMODE is changed from the PCI config
- registers */
-static void cmd646_update_irq(PCIIDEState *d)
-{
- int pci_level;
- pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
- !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
- ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
- !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
- qemu_set_irq(d->dev.irq[0], pci_level);
-}
-
-/* the PCI irq level is the logical OR of the two channels */
-static void cmd646_set_irq(void *opaque, int channel, int level)
-{
- PCIIDEState *d = opaque;
- int irq_mask;
-
- irq_mask = MRDMODE_INTR_CH0 << channel;
- if (level)
- d->dev.config[MRDMODE] |= irq_mask;
- else
- d->dev.config[MRDMODE] &= ~irq_mask;
- cmd646_update_irq(d);
-}
-
-static void cmd646_reset(void *opaque)
-{
- PCIIDEState *d = opaque;
- unsigned int i;
-
- for (i = 0; i < 2; i++)
- ide_dma_cancel(&d->bmdma[i]);
-}
-
-/* CMD646 PCI IDE controller */
-void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
- int secondary_ide_enabled)
-{
- PCIIDEState *d;
- uint8_t *pci_conf;
- qemu_irq *irq;
-
- d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
- sizeof(PCIIDEState),
- -1,
- NULL, NULL);
- d->type = IDE_TYPE_CMD646;
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
-
- pci_conf[0x08] = 0x07; // IDE controller revision
- pci_conf[0x09] = 0x8f;
-
- pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- pci_conf[0x51] = 0x04; // enable IDE0
- if (secondary_ide_enabled) {
- /* XXX: if not enabled, really disable the seconday IDE controller */
- pci_conf[0x51] |= 0x08; /* enable IDE1 */
+const VMStateDescription vmstate_ide_pci = {
+ .name = "ide",
+ .version_id = 3,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = ide_pci_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_PCI_DEVICE(dev, PCIIDEState),
+ VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
+ vmstate_bmdma, BMDMAState),
+ VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
+ VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
+ VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
+ VMSTATE_END_OF_LIST()
}
+};
- pci_register_bar((PCIDevice *)d, 0, 0x8,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 1, 0x4,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 2, 0x8,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 3, 0x4,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- pci_conf[0x3d] = 0x01; // interrupt on pin 1
-
- irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]);
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]);
-
- register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
- qemu_register_reset(cmd646_reset, d);
- cmd646_reset(d);
-}
-
-static void piix3_reset(void *opaque)
-{
- PCIIDEState *d = opaque;
- uint8_t *pci_conf = d->dev.config;
- int i;
-
- for (i = 0; i < 2; i++)
- ide_dma_cancel(&d->bmdma[i]);
-
- pci_conf[0x04] = 0x00;
- pci_conf[0x05] = 0x00;
- pci_conf[0x06] = 0x80; /* FBC */
- pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
- pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
-}
-
-/* hd_table must contain 4 block drivers */
-/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
-void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic)
+void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
{
- PCIIDEState *d;
- uint8_t *pci_conf;
+ PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
+ static const int bus[4] = { 0, 0, 1, 1 };
+ static const int unit[4] = { 0, 1, 0, 1 };
int i;
- /* register a function 1 of PIIX3 */
- d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
- sizeof(PCIIDEState),
- devfn,
- NULL, NULL);
- d->type = IDE_TYPE_PIIX3;
-
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
- pci_conf[0x09] = 0x80; // legacy ATA mode
- pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- qemu_register_reset(piix3_reset, d);
- piix3_reset(d);
-
- pci_register_bar((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], isa_reserve_irq(14));
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], isa_reserve_irq(15));
- ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->bus[1], 0x170, 0x376);
-
- for (i = 0; i < 4; i++)
- if (hd_table[i])
- hd_table[i]->private = &d->dev;
-
- register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
-}
-
-/* hd_table must contain 4 block drivers */
-/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
-void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic)
-{
- PCIIDEState *d;
- uint8_t *pci_conf;
-
- /* register a function 1 of PIIX4 */
- d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
- sizeof(PCIIDEState),
- devfn,
- NULL, NULL);
- d->type = IDE_TYPE_PIIX4;
-
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
- pci_conf[0x09] = 0x80; // legacy ATA mode
- pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- qemu_register_reset(piix3_reset, d);
- piix3_reset(d);
-
- pci_register_bar((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- /*
- * These should call isa_reserve_irq() instead when MIPS supports it
- */
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
- ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->bus[1], 0x170, 0x376);
-
- register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
+ for (i = 0; i < 4; i++) {
+ if (hd_table[i] == NULL)
+ continue;
+ ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
+ }
}
-
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