Sparc64: fix PCI probe problems

[qemu.git] / hw / apb_pci.c

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index f2ed136fda2740d1a74410d74fc6408a846b040a..a72c6568181e9bc0110c91ee4652cf5e939c5d05 100644 (file)
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -104,6 +104,82 @@ static CPUReadMemoryFunc * const apb_config_read[] = {
     &apb_config_readl,
 };
 
+static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
+                                 uint32_t val, int size)
+{
+    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
+    pci_data_write(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31), val,
+                   size);
+}
+
+static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
+                                    int size)
+{
+    uint32_t ret;
+
+    ret = pci_data_read(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31),
+                        size);
+    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
+    return ret;
+}
+
+static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr,
+                                  uint32_t val)
+{
+    APBState *s = opaque;
+
+    apb_pci_config_write(s, addr, bswap32(val), 4);
+}
+
+static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr,
+                                  uint32_t val)
+{
+    APBState *s = opaque;
+
+    apb_pci_config_write(s, addr, bswap16(val), 2);
+}
+
+static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr,
+                                  uint32_t val)
+{
+    APBState *s = opaque;
+
+    apb_pci_config_write(s, addr, val, 1);
+}
+
+static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr)
+{
+    APBState *s = opaque;
+
+    return bswap32(apb_pci_config_read(s, addr, 4));
+}
+
+static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr)
+{
+    APBState *s = opaque;
+
+    return bswap16(apb_pci_config_read(s, addr, 2));
+}
+
+static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr)
+{
+    APBState *s = opaque;
+
+    return apb_pci_config_read(s, addr, 1);
+}
+
+static CPUWriteMemoryFunc * const apb_pci_config_writes[] = {
+    &apb_pci_config_writeb,
+    &apb_pci_config_writew,
+    &apb_pci_config_writel,
+};
+
+static CPUReadMemoryFunc * const apb_pci_config_reads[] = {
+    &apb_pci_config_readb,
+    &apb_pci_config_readw,
+    &apb_pci_config_readl,
+};
+
 static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
 {
@@ -182,6 +258,25 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
     qemu_set_irq(pic[irq_num], level);
 }
 
+static void apb_pci_bridge_init(PCIBus *b)
+{
+    PCIDevice *dev = pci_bridge_get_device(b);
+
+    /*
+     * command register:
+     * According to PCI bridge spec, after reset
+     *   bus master bit is off
+     *   memory space enable bit is off
+     * According to manual (805-1251.pdf).
+     *   the reset value should be zero unless the boot pin is tied high
+     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
+     */
+    pci_set_word(dev->config + PCI_COMMAND,
+                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+    dev->config[PCI_LATENCY_TIMER] = 0x10;
+    dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
+}
+
 PCIBus *pci_apb_init(target_phys_addr_t special_base,
                      target_phys_addr_t mem_base,
                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
@@ -195,10 +290,10 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
     qdev_init_nofail(dev);
     s = sysbus_from_qdev(dev);
     /* apb_config */
-    sysbus_mmio_map(s, 0, special_base + 0x2000ULL);
+    sysbus_mmio_map(s, 0, special_base);
     /* pci_ioport */
     sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
-    /* mem_config: XXX size should be 4G-prom */
+    /* pci_config */
     sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
     /* mem_data */
     sysbus_mmio_map(s, 3, mem_base);
@@ -206,16 +301,21 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
     d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                          pci_apb_set_irq, pci_pbm_map_irq, pic,
                                          0, 32);
+    pci_bus_set_mem_base(d->host_state.bus, mem_base);
+
     pci_create_simple(d->host_state.bus, 0, "pbm");
     /* APB secondary busses */
     *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
                             PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                             pci_apb_map_irq,
                             "Advanced PCI Bus secondary bridge 1");
+    apb_pci_bridge_init(*bus2);
+
     *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
                             PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                             pci_apb_map_irq,
                             "Advanced PCI Bus secondary bridge 2");
+    apb_pci_bridge_init(*bus3);
 
     return d->host_state.bus;
 }
@@ -224,20 +324,21 @@ static int pci_pbm_init_device(SysBusDevice *dev)
 {
 
     APBState *s;
-    int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
+    int pci_mem_data, apb_config, pci_ioport, pci_config;
 
     s = FROM_SYSBUS(APBState, dev);
     /* apb_config */
     apb_config = cpu_register_io_memory(apb_config_read,
                                         apb_config_write, s);
-    sysbus_init_mmio(dev, 0x40ULL, apb_config);
+    sysbus_init_mmio(dev, 0x10000ULL, apb_config);
     /* pci_ioport */
     pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                           pci_apb_iowrite, s);
     sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
-    /* mem_config  */
-    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
-    sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
+    /* pci_config */
+    pci_config = cpu_register_io_memory(apb_pci_config_reads,
+                                        apb_pci_config_writes, s);
+    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
     /* mem_data */
     pci_mem_data = pci_host_data_register_mmio(&s->host_state);
     sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);