* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "hw/sparc/sun4m_iommu.h"
-#include "hw/timer/m48t59.h"
+#include "hw/rtc/m48t59.h"
+#include "migration/vmstate.h"
#include "hw/sparc/sparc32_dma.h"
#include "hw/block/fdc.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/scsi/esp.h"
#include "hw/nvram/sun_nvram.h"
+#include "hw/qdev-properties.h"
#include "hw/nvram/chrp_nvram.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/char/escc.h"
-#include "hw/empty_slot.h"
+#include "hw/misc/empty_slot.h"
+#include "hw/misc/unimp.h"
+#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
#include "trace.h"
+#include "qom/object.h"
/*
* Sun4m architecture was used in the following machines:
memset(image, '\0', sizeof(image));
/* OpenBIOS nvram variables partition */
- sysp_end = chrp_nvram_create_system_partition(image, 0);
+ sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
/* Free space partition */
chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
{
}
-static void main_cpu_reset(void *opaque)
-{
- SPARCCPU *cpu = opaque;
- CPUState *cs = CPU(cpu);
-
- cpu_reset(cs);
- cs->halted = 0;
-}
-
-static void secondary_cpu_reset(void *opaque)
+static void sun4m_cpu_reset(void *opaque)
{
SPARCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
cpu_reset(cs);
- cs->halted = 1;
}
static void cpu_halt_signal(void *opaque, int irq, int level)
#endif
kernel_size = load_elf(kernel_filename, NULL,
translate_kernel_address, NULL,
- NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
+ NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
+ dev = qdev_new(TYPE_SUN4M_IOMMU);
qdev_prop_set_uint32(dev, "version", version);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, addr);
SysBusESPState *esp;
SysBusPCNetState *lance;
- dma = qdev_create(NULL, TYPE_SPARC32_DMA);
- qdev_init_nofail(dma);
+ dma = qdev_new(TYPE_SPARC32_DMA);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
SysBusDevice *s;
unsigned int i, j;
- dev = qdev_create(NULL, "slavio_intctl");
- qdev_init_nofail(dev);
+ dev = qdev_new("slavio_intctl");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < MAX_CPUS; i++) {
for (j = 0; j < MAX_PILS; j++) {
SysBusDevice *s;
unsigned int i;
- dev = qdev_create(NULL, "slavio_timer");
+ dev = qdev_new("slavio_timer");
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, master_irq);
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "slavio_misc");
- qdev_init_nofail(dev);
+ dev = qdev_new("slavio_misc");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
if (base) {
/* 8 bit registers */
/* Slavio control */
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "eccmemctl");
+ dev = qdev_new("eccmemctl");
qdev_prop_set_uint32(dev, "version", version);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, base);
if (version == 0) { // SS-600MP only
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "apc");
- qdev_init_nofail(dev);
+ dev = qdev_new("apc");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* Power management (APC) XXX: not a Slavio device */
sysbus_mmio_map(s, 0, power_base);
sysbus_connect_irq(s, 0, cpu_halt);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "SUNW,tcx");
+ dev = qdev_new("SUNW,tcx");
qdev_prop_set_uint32(dev, "vram_size", vram_size);
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* 10/ROM : FCode ROM */
sysbus_mmio_map(s, 0, addr);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "cgthree");
+ dev = qdev_new("cgthree");
qdev_prop_set_uint32(dev, "vram-size", vram_size);
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* FCode ROM */
sysbus_mmio_map(s, 0, addr);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_MACIO_ID_REGISTER);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
address_space_write_rom(&address_space_memory, addr,
idreg_data, sizeof(idreg_data));
}
+typedef struct IDRegState IDRegState;
#define MACIO_ID_REGISTER(obj) \
OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
-typedef struct IDRegState {
+struct IDRegState {
SysBusDevice parent_obj;
MemoryRegion mem;
-} IDRegState;
+};
static void idreg_realize(DeviceState *ds, Error **errp)
{
};
#define TYPE_TCX_AFX "tcx_afx"
+typedef struct AFXState AFXState;
#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
-typedef struct AFXState {
+struct AFXState {
SysBusDevice parent_obj;
MemoryRegion mem;
-} AFXState;
+};
/* SS-5 TCX AFX register */
static void afx_init(hwaddr addr)
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_TCX_AFX);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_TCX_AFX);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
};
#define TYPE_OPENPROM "openprom"
+typedef struct PROMState PROMState;
#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
-typedef struct PROMState {
+struct PROMState {
SysBusDevice parent_obj;
MemoryRegion prom;
-} PROMState;
+};
/* Boot PROM (OpenBIOS) */
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
char *filename;
int ret;
- dev = qdev_create(NULL, TYPE_OPENPROM);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_OPENPROM);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
if (filename) {
ret = load_elf(filename, NULL,
translate_prom_address, &addr, NULL,
- NULL, NULL, 1, EM_SPARC, 0, 0);
+ NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
if (ret < 0 || ret > PROM_SIZE_MAX) {
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = prom_properties;
+ device_class_set_props(dc, prom_properties);
dc->realize = prom_realize;
}
};
#define TYPE_SUN4M_MEMORY "memory"
+typedef struct RamDevice RamDevice;
#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
-typedef struct RamDevice {
+struct RamDevice {
SysBusDevice parent_obj;
-
- MemoryRegion ram;
- uint64_t size;
-} RamDevice;
+ HostMemoryBackend *memdev;
+};
/* System RAM */
static void ram_realize(DeviceState *dev, Error **errp)
{
RamDevice *d = SUN4M_RAM(dev);
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
- memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
- d->size);
- sysbus_init_mmio(sbd, &d->ram);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
}
-static void ram_init(hwaddr addr, ram_addr_t RAM_size,
- uint64_t max_mem)
+static void ram_initfn(Object *obj)
{
- DeviceState *dev;
- SysBusDevice *s;
- RamDevice *d;
-
- /* allocate RAM */
- if ((uint64_t)RAM_size > max_mem) {
- error_report("Too much memory for this machine: %" PRId64 ","
- " maximum %" PRId64,
- RAM_size / MiB, max_mem / MiB);
- exit(1);
- }
- dev = qdev_create(NULL, "memory");
- s = SYS_BUS_DEVICE(dev);
-
- d = SUN4M_RAM(dev);
- d->size = RAM_size;
- qdev_init_nofail(dev);
-
- sysbus_mmio_map(s, 0, addr);
+ RamDevice *d = SUN4M_RAM(obj);
+ object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
+ (Object **)&d->memdev,
+ object_property_allow_set_link,
+ OBJ_PROP_LINK_STRONG);
+ object_property_set_description(obj, "memdev", "Set RAM backend"
+ "Valid value is ID of a hostmem backend");
}
-static Property ram_properties[] = {
- DEFINE_PROP_UINT64("size", RamDevice, size, 0),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void ram_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ram_realize;
- dc->props = ram_properties;
}
static const TypeInfo ram_info = {
.name = TYPE_SUN4M_MEMORY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RamDevice),
+ .instance_init = ram_initfn,
.class_init = ram_class_init,
};
static void cpu_devinit(const char *cpu_type, unsigned int id,
uint64_t prom_addr, qemu_irq **cpu_irqs)
{
- CPUState *cs;
SPARCCPU *cpu;
CPUSPARCState *env;
- cpu = SPARC_CPU(cpu_create(cpu_type));
+ cpu = SPARC_CPU(object_new(cpu_type));
env = &cpu->env;
cpu_sparc_set_id(env, id);
- if (id == 0) {
- qemu_register_reset(main_cpu_reset, cpu);
- } else {
- qemu_register_reset(secondary_cpu_reset, cpu);
- cs = CPU(cpu);
- cs->halted = 1;
- }
+ qemu_register_reset(sun4m_cpu_reset, cpu);
+ object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
+ &error_fatal);
+ qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
env->prom_addr = prom_addr;
}
SysBusDevice *s;
unsigned int smp_cpus = machine->smp.cpus;
unsigned int max_cpus = machine->smp.max_cpus;
+ Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
+ TYPE_MEMORY_BACKEND, NULL);
+
+ if (machine->ram_size > hwdef->max_mem) {
+ error_report("Too much memory for this machine: %" PRId64 ","
+ " maximum %" PRId64,
+ machine->ram_size / MiB, hwdef->max_mem / MiB);
+ exit(1);
+ }
/* init CPUs */
for(i = 0; i < smp_cpus; i++) {
for (i = smp_cpus; i < MAX_CPUS; i++)
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
+ /* Create and map RAM frontend */
+ dev = qdev_new("memory");
+ object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
- /* set up devices */
- ram_init(0, machine->ram_size, hwdef->max_mem);
/* models without ECC don't trap when missing ram is accessed */
if (!hwdef->ecc_base) {
- empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
+ empty_slot_init("ecc", machine->ram_size,
+ hwdef->max_mem - machine->ram_size);
}
prom_init(hwdef->slavio_base, bios_name);
Software shouldn't use aliased addresses, neither should it crash
when does. Using empty_slot instead of aliasing can help with
debugging such accesses */
- empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
+ empty_slot_init("iommu.alias",
+ hwdef->iommu_pad_base, hwdef->iommu_pad_len);
}
sparc32_dma_init(hwdef->dma_base,
for (i = 0; i < MAX_VSIMMS; i++) {
/* vsimm registers probed by OBP */
if (hwdef->vsimm[i].reg_base) {
- empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
+ char *name = g_strdup_printf("vsimm[%d]", i);
+ empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
+ g_free(name);
}
}
if (hwdef->sx_base) {
- empty_slot_init(hwdef->sx_base, 0x2000);
+ create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
}
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
- dev = qdev_create(NULL, TYPE_ESCC);
+ dev = qdev_new(TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_prop_set_chr(dev, "chrA", NULL);
qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[14]);
sysbus_connect_irq(s, 1, slavio_irq[14]);
sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
- dev = qdev_create(NULL, TYPE_ESCC);
+ dev = qdev_new(TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[15]);
sysbus_connect_irq(s, 1, slavio_irq[15]);
sysbus_mmio_map(s, 0, hwdef->serial_base);
if (hwdef->dbri_base) {
/* ISDN chip with attached CS4215 audio codec */
/* prom space */
- empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
+ create_unimplemented_device("SUNW,DBRI.prom",
+ hwdef->dbri_base + 0x1000, 0x30);
/* reg space */
- empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
+ create_unimplemented_device("SUNW,DBRI",
+ hwdef->dbri_base + 0x10000, 0x100);
}
if (hwdef->bpp_base) {
/* parallel port */
- empty_slot_init(hwdef->bpp_base, 0x20);
+ create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
}
initrd_size = 0;
ecc_init(hwdef->ecc_base, slavio_irq[28],
hwdef->ecc_version);
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
- OBJECT(fw_cfg), NULL);
- qdev_init_nofail(dev);
+ OBJECT(fw_cfg));
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
- fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
mc->desc = "Sun4m platform, SPARCstation 5";
mc->init = ss5_init;
mc->block_default_type = IF_SCSI;
- mc->is_default = 1;
+ mc->is_default = true;
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo ss5_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo ss10_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo ss600mp_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo ss20_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo voyager_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo ss_lx_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo ss4_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo scls_type = {
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static const TypeInfo sbook_type = {
projects / qemu.git / blobdiff