tcg/arm: Implement movcond_i32

[qemu.git] / tcg / arm / tcg-target.h

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 4b2b0be14c30040deaf43f6a1b1836f33118af72..0df33520f8a88be2e61e9789a7ab146c53730114 100644 (file)
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -24,11 +24,10 @@
  */
 #define TCG_TARGET_ARM 1
 
  */
 #define TCG_TARGET_ARM 1
 

-#define TCG_TARGET_REG_BITS 32

 #undef TCG_TARGET_WORDS_BIGENDIAN
 #undef TCG_TARGET_STACK_GROWSUP
 
 #undef TCG_TARGET_WORDS_BIGENDIAN
 #undef TCG_TARGET_STACK_GROWSUP
 

-enum {
+typedef enum {

     TCG_REG_R0 = 0,
     TCG_REG_R1,
     TCG_REG_R2,
     TCG_REG_R0 = 0,
     TCG_REG_R1,
     TCG_REG_R2,


@@ -44,41 +43,46 @@ enum {
     TCG_REG_R12,
     TCG_REG_R13,
     TCG_REG_R14,
     TCG_REG_R12,
     TCG_REG_R13,
     TCG_REG_R14,

-};
+    TCG_REG_PC,
+} TCGReg;

 
 

-#define TCG_TARGET_NB_REGS 15
+#define TCG_TARGET_NB_REGS 16

 
 #define TCG_CT_CONST_ARM 0x100
 
 /* used for function call generation */
 #define TCG_REG_CALL_STACK             TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN         8
 
 #define TCG_CT_CONST_ARM 0x100
 
 /* used for function call generation */
 #define TCG_REG_CALL_STACK             TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN         8

+#define TCG_TARGET_CALL_ALIGN_ARGS     1

 #define TCG_TARGET_CALL_STACK_OFFSET   0
 
 /* optional instructions */
 #define TCG_TARGET_CALL_STACK_OFFSET   0
 
 /* optional instructions */

-#define TCG_TARGET_HAS_div2_i32
-#define TCG_TARGET_HAS_ext8s_i32
-#define TCG_TARGET_HAS_ext16s_i32
-// #define TCG_TARGET_HAS_ext8u_i32
-// #define TCG_TARGET_HAS_ext16u_i32
-// #define TCG_TARGET_HAS_bswap16_i32
-// #define TCG_TARGET_HAS_bswap32_i32
-#define TCG_TARGET_HAS_not_i32
-#define TCG_TARGET_HAS_neg_i32
-// #define TCG_TARGET_HAS_rot_i32
-#define TCG_TARGET_HAS_andc_i32
-// #define TCG_TARGET_HAS_orc_i32
+#define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_ext8s_i32        1
+#define TCG_TARGET_HAS_ext16s_i32       1
+#define TCG_TARGET_HAS_ext8u_i32        0 /* and r0, r1, #0xff */
+#define TCG_TARGET_HAS_ext16u_i32       1
+#define TCG_TARGET_HAS_bswap16_i32      1
+#define TCG_TARGET_HAS_bswap32_i32      1
+#define TCG_TARGET_HAS_not_i32          1
+#define TCG_TARGET_HAS_neg_i32          1
+#define TCG_TARGET_HAS_rot_i32          1
+#define TCG_TARGET_HAS_andc_i32         1
+#define TCG_TARGET_HAS_orc_i32          0
+#define TCG_TARGET_HAS_eqv_i32          0
+#define TCG_TARGET_HAS_nand_i32         0
+#define TCG_TARGET_HAS_nor_i32          0
+#define TCG_TARGET_HAS_deposit_i32      0
+#define TCG_TARGET_HAS_movcond_i32      1

 
 #define TCG_TARGET_HAS_GUEST_BASE
 
 enum {
 
 #define TCG_TARGET_HAS_GUEST_BASE
 
 enum {

-    /* Note: must be synced with dyngen-exec.h */
-    TCG_AREG0 = TCG_REG_R7,
-    TCG_AREG1 = TCG_REG_R4,
-    TCG_AREG2 = TCG_REG_R5,
+    TCG_AREG0 = TCG_REG_R6,

 };
 
 };
 

-static inline void flush_icache_range(unsigned long start, unsigned long stop)
+static inline void flush_icache_range(tcg_target_ulong start,
+                                      tcg_target_ulong stop)

 {
 #if QEMU_GNUC_PREREQ(4, 1)
     __builtin___clear_cache((char *) start, (char *) stop);
 {
 #if QEMU_GNUC_PREREQ(4, 1)
     __builtin___clear_cache((char *) start, (char *) stop);