Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemu

[qemu.git] / hw / mcf5208.c

diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index dae9a61c2c0783ec92ad8a8a5d5792ba535523a8..ee25b1b38765237e54265d87186c96e5a0ec3970 100644 (file)
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -3,14 +3,18 @@
  *
  * Copyright (c) 2007 CodeSourcery.
  *
  *
  * Copyright (c) 2007 CodeSourcery.
  *

- * This code is licenced under the GPL
+ * This code is licensed under the GPL

  */
 #include "hw.h"
 #include "mcf.h"
 #include "qemu-timer.h"
  */
 #include "hw.h"
 #include "mcf.h"
 #include "qemu-timer.h"

+#include "ptimer.h"

 #include "sysemu.h"
 #include "net.h"
 #include "boards.h"
 #include "sysemu.h"
 #include "net.h"
 #include "boards.h"

+#include "loader.h"
+#include "elf.h"
+#include "exec-memory.h"

 
 #define SYS_FREQ 66000000
 
 
 #define SYS_FREQ 66000000
 


@@ -25,6 +29,7 @@
 #define PCSR_PRE_MASK   0x0f00
 
 typedef struct {
 #define PCSR_PRE_MASK   0x0f00
 
 typedef struct {

+    MemoryRegion iomem;

     qemu_irq irq;
     ptimer_state *timer;
     uint16_t pcsr;
     qemu_irq irq;
     ptimer_state *timer;
     uint16_t pcsr;


@@ -41,7 +46,7 @@ static void m5208_timer_update(m5208_timer_state *s)
 }
 
 static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
 }
 
 static void m5208_timer_write(void *opaque, target_phys_addr_t offset,

-                              uint32_t value)
+                              uint64_t value, unsigned size)

 {
     m5208_timer_state *s = (m5208_timer_state *)opaque;
     int prescale;
 {
     m5208_timer_state *s = (m5208_timer_state *)opaque;
     int prescale;


@@ -89,8 +94,7 @@ static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
     case 4:
         break;
     default:
     case 4:
         break;
     default:

-        cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n",
-                  (int)offset);
+        hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);

         break;
     }
     m5208_timer_update(s);
         break;
     }
     m5208_timer_update(s);


@@ -103,7 +107,8 @@ static void m5208_timer_trigger(void *opaque)
     m5208_timer_update(s);
 }
 
     m5208_timer_update(s);
 }
 

-static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
+                                 unsigned size)

 {
     m5208_timer_state *s = (m5208_timer_state *)opaque;
     switch (addr) {
 {
     m5208_timer_state *s = (m5208_timer_state *)opaque;
     switch (addr) {


@@ -114,25 +119,19 @@ static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
     case 4:
         return ptimer_get_count(s->timer);
     default:
     case 4:
         return ptimer_get_count(s->timer);
     default:

-        cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n",
-                  (int)addr);
+        hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);

         return 0;
     }
 }
 
         return 0;
     }
 }
 

-static CPUReadMemoryFunc *m5208_timer_readfn[] = {
-   m5208_timer_read,
-   m5208_timer_read,
-   m5208_timer_read
+static const MemoryRegionOps m5208_timer_ops = {
+    .read = m5208_timer_read,
+    .write = m5208_timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 };
 

-static CPUWriteMemoryFunc *m5208_timer_writefn[] = {
-   m5208_timer_write,
-   m5208_timer_write,
-   m5208_timer_write
-};
-
-static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
+static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
+                               unsigned size)

 {
     switch (addr) {
     case 0x110: /* SDCS0 */
 {
     switch (addr) {
     case 0x110: /* SDCS0 */


@@ -148,65 +147,59 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
         return 0;
 
     default:
         return 0;
 
     default:

-        cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
-                  (int)addr);
+        hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);

         return 0;
     }
 }
 
 static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
         return 0;
     }
 }
 
 static void m5208_sys_write(void *opaque, target_phys_addr_t addr,

-                            uint32_t value)
+                            uint64_t value, unsigned size)

 {
 {

-    cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
-              (int)addr);
+    hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);

 }
 
 }
 

-static CPUReadMemoryFunc *m5208_sys_readfn[] = {
-   m5208_sys_read,
-   m5208_sys_read,
-   m5208_sys_read
-};
-
-static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
-   m5208_sys_write,
-   m5208_sys_write,
-   m5208_sys_write
+static const MemoryRegionOps m5208_sys_ops = {
+    .read = m5208_sys_read,
+    .write = m5208_sys_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 };
 

-static void mcf5208_sys_init(qemu_irq *pic)
+static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)

 {
 {

-    int iomemtype;
+    MemoryRegion *iomem = g_new(MemoryRegion, 1);

     m5208_timer_state *s;
     QEMUBH *bh;
     int i;
 
     m5208_timer_state *s;
     QEMUBH *bh;
     int i;
 

-    iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
-                                       m5208_sys_writefn, NULL);

     /* SDRAMC.  */
     /* SDRAMC.  */

-    cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
+    memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
+    memory_region_add_subregion(address_space, 0xfc0a8000, iomem);

     /* Timers.  */
     for (i = 0; i < 2; i++) {
     /* Timers.  */
     for (i = 0; i < 2; i++) {

-        s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));
+        s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));

         bh = qemu_bh_new(m5208_timer_trigger, s);
         s->timer = ptimer_init(bh);
         bh = qemu_bh_new(m5208_timer_trigger, s);
         s->timer = ptimer_init(bh);

-        iomemtype = cpu_register_io_memory(0, m5208_timer_readfn,
-                                           m5208_timer_writefn, s);
-        cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
-                                     iomemtype);
+        memory_region_init_io(&s->iomem, &m5208_timer_ops, s,
+                              "m5208-timer", 0x00004000);
+        memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
+                                    &s->iomem);

         s->irq = pic[4 + i];
     }
 }
 
         s->irq = pic[4 + i];
     }
 }
 

-static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
+static void mcf5208evb_init(ram_addr_t ram_size,

                      const char *boot_device,
                      const char *kernel_filename, const char *kernel_cmdline,
                      const char *initrd_filename, const char *cpu_model)
 {
                      const char *boot_device,
                      const char *kernel_filename, const char *kernel_cmdline,
                      const char *initrd_filename, const char *cpu_model)
 {

-    CPUState *env;
+    CPUM68KState *env;

     int kernel_size;
     uint64_t elf_entry;
     int kernel_size;
     uint64_t elf_entry;

-    target_ulong entry;
+    target_phys_addr_t entry;

     qemu_irq *pic;
     qemu_irq *pic;

+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *ram = g_new(MemoryRegion, 1);
+    MemoryRegion *sram = g_new(MemoryRegion, 1);

 
     if (!cpu_model)
         cpu_model = "m5208";
 
     if (!cpu_model)
         cpu_model = "m5208";


@@ -220,29 +213,32 @@ static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
     env->vbr = 0;
     /* TODO: Configure BARs.  */
 
     env->vbr = 0;
     /* TODO: Configure BARs.  */
 

-    /* DRAM at 0x20000000 */
-    cpu_register_physical_memory(0x40000000, ram_size,
-        qemu_ram_alloc(ram_size) | IO_MEM_RAM);
+    /* DRAM at 0x40000000 */
+    memory_region_init_ram(ram, "mcf5208.ram", ram_size);
+    vmstate_register_ram_global(ram);
+    memory_region_add_subregion(address_space_mem, 0x40000000, ram);

 
     /* Internal SRAM.  */
 
     /* Internal SRAM.  */

-    cpu_register_physical_memory(0x80000000, 16384,
-        qemu_ram_alloc(16384) | IO_MEM_RAM);
+    memory_region_init_ram(sram, "mcf5208.sram", 16384);
+    vmstate_register_ram_global(sram);
+    memory_region_add_subregion(address_space_mem, 0x80000000, sram);

 
     /* Internal peripherals.  */
 
     /* Internal peripherals.  */

-    pic = mcf_intc_init(0xfc048000, env);
+    pic = mcf_intc_init(address_space_mem, 0xfc048000, env);

 
 

-    mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
-    mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
-    mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
+    mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
+    mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
+    mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);

 
 

-    mcf5208_sys_init(pic);
+    mcf5208_sys_init(address_space_mem, pic);

 
     if (nb_nics > 1) {
         fprintf(stderr, "Too many NICs\n");
         exit(1);
     }
 
     if (nb_nics > 1) {
         fprintf(stderr, "Too many NICs\n");
         exit(1);
     }

-    if (nd_table[0].vlan)
-        mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
+    if (nd_table[0].used)
+        mcf_fec_init(address_space_mem, &nd_table[0],
+                     0xfc030000, pic + 36);

 
     /*  0xfc000000 SCM.  */
     /*  0xfc004000 XBS.  */
 
     /*  0xfc000000 SCM.  */
     /*  0xfc004000 XBS.  */


@@ -272,14 +268,16 @@ static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
         exit(1);
     }
 
         exit(1);
     }
 

-    kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
+    kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
+                           NULL, NULL, 1, ELF_MACHINE, 0);

     entry = elf_entry;
     if (kernel_size < 0) {
         kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
     }
     if (kernel_size < 0) {
     entry = elf_entry;
     if (kernel_size < 0) {
         kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
     }
     if (kernel_size < 0) {

-        kernel_size = load_image(kernel_filename, phys_ram_base);
-        entry = 0x20000000;
+        kernel_size = load_image_targphys(kernel_filename, 0x40000000,
+                                          ram_size);
+        entry = 0x40000000;

     }
     if (kernel_size < 0) {
         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
     }
     if (kernel_size < 0) {
         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);


@@ -289,9 +287,16 @@ static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
     env->pc = entry;
 }
 
     env->pc = entry;
 }
 

-QEMUMachine mcf5208evb_machine = {
+static QEMUMachine mcf5208evb_machine = {

     .name = "mcf5208evb",
     .desc = "MCF5206EVB",
     .init = mcf5208evb_init,
     .name = "mcf5208evb",
     .desc = "MCF5206EVB",
     .init = mcf5208evb_init,

-    .ram_require = 16384,
+    .is_default = 1,

 };
 };

+
+static void mcf5208evb_machine_init(void)
+{
+    qemu_register_machine(&mcf5208evb_machine);
+}
+
+machine_init(mcf5208evb_machine_init);