char: rename qemu_chr_read() -> qemu_chr_be_write()

[qemu.git] / target-cris / cpu.h

diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index d086221d3f1dbd7ed687300f0aa9470fbcfbb2cd..8ae0ce3ef329fa5b90e26400419a3207d78c5795 100644 (file)
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -15,14 +15,15 @@
  * General Public License for more details.
  *
  * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef CPU_CRIS_H
 #define CPU_CRIS_H
 
 #define TARGET_LONG_BITS 32
 
+#define CPUState struct CPUCRISState
+
 #include "cpu-defs.h"
 
 #define TARGET_HAS_ICE 1
@@ -35,6 +36,9 @@
 #define EXCP_IRQ        4
 #define EXCP_BREAK      5
 
+/* CRIS-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
+
 /* Register aliases. R0 - R15 */
 #define R_FP  8
 #define R_SP  14
@@ -48,6 +52,7 @@
 #define PR_WZ  4
 #define PR_EXS 5
 #define PR_EDA 6
+#define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
 #define PR_MOF 7
 #define PR_DZ  8
 #define PR_EBP 9
@@ -61,12 +66,11 @@
 /* CPU flags.  */
 #define Q_FLAG 0x80000000
 #define M_FLAG 0x40000000
+#define PFIX_FLAG 0x800      /* CRISv10 Only.  */
 #define S_FLAG 0x200
 #define R_FLAG 0x100
 #define P_FLAG 0x80
 #define U_FLAG 0x40
-#define P_FLAG 0x80
-#define U_FLAG 0x40
 #define I_FLAG 0x20
 #define X_FLAG 0x10
 #define N_FLAG 0x08
@@ -93,9 +97,6 @@
 #define CC_A   14
 #define CC_P   15
 
-/* Internal flags for the implementation.  */
-#define F_DELAYSLOT 1
-
 #define NB_MMU_MODES 2
 
 typedef struct CPUCRISState {
@@ -103,7 +104,7 @@ typedef struct CPUCRISState {
        /* P0 - P15 are referred to as special registers in the docs.  */
        uint32_t pregs[16];
 
-       /* Pseudo register for the PC. Not directly accessable on CRIS.  */
+       /* Pseudo register for the PC. Not directly accessible on CRIS.  */
        uint32_t pc;
 
        /* Pseudo register for the kernel stack.  */
@@ -125,7 +126,8 @@ typedef struct CPUCRISState {
        /* X flag at the time of cc snapshot.  */
        int cc_x;
 
-       int interrupt_request;
+       /* CRIS has certain insns that lockout interrupts.  */
+       int locked_irq;
        int interrupt_vector;
        int fault_vector;
        int trap_vector;
@@ -156,9 +158,10 @@ typedef struct CPUCRISState {
                uint32_t lo;
        } tlbsets[2][4][16];
 
-       int user_mode_only;
-
        CPU_COMMON
+
+       /* Members after CPU_COMMON are preserved across resets.  */
+       void *load_info;
 } CPUCRISState;
 
 CPUCRISState *cpu_cris_init(const char *cpu_model);
@@ -170,8 +173,6 @@ void do_interrupt(CPUCRISState *env);
    is returned if the signal was handled by the virtual CPU.  */
 int cpu_cris_signal_handler(int host_signum, void *pinfo,
                            void *puc);
-void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
-                          int is_asi);
 
 enum {
     CC_OP_DYNAMIC, /* Use env->cc_op  */
@@ -189,6 +190,7 @@ enum {
     CC_OP_MULS,
     CC_OP_MULU,
     CC_OP_DSTEP,
+    CC_OP_MSTEP,
     CC_OP_BOUND,
 
     CC_OP_OR,
@@ -204,12 +206,16 @@ enum {
 #define TARGET_PAGE_BITS 13
 #define MMAP_SHIFT TARGET_PAGE_BITS
 
-#define CPUState CPUCRISState
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+
 #define cpu_init cpu_cris_init
 #define cpu_exec cpu_cris_exec
 #define cpu_gen_code cpu_cris_gen_code
 #define cpu_signal_handler cpu_cris_signal_handler
 
+#define CPU_SAVE_VERSION 1
+
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user
@@ -219,6 +225,10 @@ static inline int cpu_mmu_index (CPUState *env)
        return !!(env->pregs[PR_CCS] & U_FLAG);
 }
 
+int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+                              int mmu_idx);
+#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
+
 #if defined(CONFIG_USER_ONLY)
 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 {
@@ -228,6 +238,11 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 }
 #endif
 
+static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
+{
+       env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
+}
+
 /* Support function regs.  */
 #define SFR_RW_GC_CFG      0][0
 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
@@ -238,7 +253,30 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 
-#define CPU_PC_FROM_TB(env, tb) env->pc = tb->pc
-
 #include "cpu-all.h"
+
+static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+                                        target_ulong *cs_base, int *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = env->dslot |
+            (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
+                                    | X_FLAG | PFIX_FLAG));
+}
+
+#define cpu_list cris_cpu_list
+void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+}
 #endif