#if defined (TARGET_PPC64)
/* PowerPC 64 definitions */
-typedef uint64_t ppc_gpr_t;
#define TARGET_LONG_BITS 64
#define TARGET_PAGE_BITS 12
#else /* defined (TARGET_PPC64) */
/* PowerPC 32 definitions */
-#if (HOST_LONG_BITS >= 64)
-/* When using 64 bits temporary registers,
- * we can use 64 bits GPR with no extra cost
- * It's even an optimization as this will prevent
- * the compiler to do unuseful masking in the micro-ops.
- */
-typedef uint64_t ppc_gpr_t;
-#else /* (HOST_LONG_BITS >= 64) */
-typedef uint32_t ppc_gpr_t;
-#endif /* (HOST_LONG_BITS >= 64) */
-
#define TARGET_LONG_BITS 32
#if defined(TARGET_PPCEMB)
void (*hea_read)(void *opaque, int spr_num);
void (*hea_write)(void *opaque, int spr_num);
#endif
- const unsigned char *name;
+ const char *name;
};
/* Altivec registers (128 bits) */
/* First are the most commonly used resources
* during translated code execution
*/
-#if (HOST_LONG_BITS == 32)
- /* temporary fixed-point registers
- * used to emulate 64 bits registers on 32 bits hosts
- */
- uint64_t t0, t1, t2;
+#if TARGET_LONG_BITS > HOST_LONG_BITS
+ target_ulong t0, t1;
+#endif
+ /* XXX: this is a temporary workaround for i386. cf translate.c comment */
+#if (TARGET_LONG_BITS > HOST_LONG_BITS) || defined(HOST_I386)
+ target_ulong t2;
#endif
- ppc_avr_t avr0, avr1, avr2;
/* general purpose registers */
- ppc_gpr_t gpr[32];
+ target_ulong gpr[32];
#if !defined(TARGET_PPC64)
/* Storage for GPR MSB, used by the SPE extension */
- ppc_gpr_t gprh[32];
+ target_ulong gprh[32];
#endif
/* LR */
target_ulong lr;
/* CTR */
target_ulong ctr;
/* condition register */
- uint8_t crf[8];
+ uint32_t crf[8];
/* XER */
- /* XXX: We use only 5 fields, but we want to keep the structure aligned */
- uint8_t xer[8];
+ target_ulong xer;
/* Reservation address */
target_ulong reserve;
/* machine state register */
target_ulong msr;
/* temporary general purpose registers */
- ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
+ target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
/* Floating point execution context */
- /* temporary float registers */
- float64 ft0;
- float64 ft1;
- float64 ft2;
float_status fp_status;
/* floating point registers */
float64 fpr[32];
ppc_avr_t avr[32];
uint32_t vscr;
/* SPE registers */
- ppc_gpr_t spe_acc;
+ target_ulong spe_acc;
float_status spe_status;
uint32_t spe_fscr;
uint32_t flags;
int error_code;
- int interrupt_request;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
/* This is the IRQ controller, which is implementation dependant
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
- int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */
void do_interrupt (CPUPPCState *env);
void ppc_hw_interrupt (CPUPPCState *env);
-void cpu_loop_exit (void);
void dump_stack (CPUPPCState *env);
#endif
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
#endif /* !defined(CONFIG_USER_ONLY) */
-target_ulong ppc_load_xer (CPUPPCState *env);
-void ppc_store_xer (CPUPPCState *env, target_ulong value);
void ppc_store_msr (CPUPPCState *env, target_ulong value);
void cpu_ppc_reset (void *opaque);
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
-const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
+const ppc_def_t *cpu_ppc_find_by_name (const char *name);
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
/* Time-base and decrementer management */
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
+#define CPU_SAVE_VERSION 3
+
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
}
#endif
-#define CPU_PC_FROM_TB(env, tb) env->nip = tb->pc
-
#include "cpu-all.h"
+#include "exec-all.h"
/*****************************************************************************/
-/* Registers definitions */
-#define XER_SO 31
-#define XER_OV 30
-#define XER_CA 29
-#define XER_CMP 8
-#define XER_BC 0
-#define xer_so env->xer[4]
-#define xer_ov env->xer[6]
-#define xer_ca env->xer[2]
-#define xer_cmp env->xer[1]
-#define xer_bc env->xer[0]
+/* CRF definitions */
+#define CRF_LT 3
+#define CRF_GT 2
+#define CRF_EQ 1
+#define CRF_SO 0
+#define CRF_CH (1 << 4)
+#define CRF_CL (1 << 3)
+#define CRF_CH_OR_CL (1 << 2)
+#define CRF_CH_AND_CL (1 << 1)
+
+/* XER definitions */
+#define XER_SO 31
+#define XER_OV 30
+#define XER_CA 29
+#define XER_CMP 8
+#define XER_BC 0
+#define xer_so ((env->xer >> XER_SO) & 1)
+#define xer_ov ((env->xer >> XER_OV) & 1)
+#define xer_ca ((env->xer >> XER_CA) & 1)
+#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
+#define xer_bc ((env->xer >> XER_BC) & 0x7F)
/* SPR definitions */
#define SPR_MQ (0x000)
/*****************************************************************************/
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->nip = tb->pc;
+}
+
+static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->nip;
+ *cs_base = 0;
+ *flags = env->hflags;
+}
+
#endif /* !defined (__CPU_PPC_H__) */
projects / qemu.git / blobdiff