omap_badwidth_write16,
};
-struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
+static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
int iomemtype;
}
/* L4 Interconnect */
-struct omap_target_agent_s {
- struct omap_l4_s *bus;
- int regions;
- struct omap_l4_region_s *start;
- target_phys_addr_t base;
- uint32_t component;
- uint32_t control;
- uint32_t status;
-};
-
-struct omap_l4_s {
- target_phys_addr_t base;
- int ta_num;
- struct omap_target_agent_s ta[0];
-};
-
-#ifdef L4_MUX_HACK
-static int omap_l4_io_entries;
-static int omap_cpu_io_entry;
-static struct omap_l4_entry {
- CPUReadMemoryFunc * const *mem_read;
- CPUWriteMemoryFunc * const *mem_write;
- void *opaque;
-} *omap_l4_io_entry;
-static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
-static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
-static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
-static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
-static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
-static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
-static void **omap_l4_io_opaque;
-
-int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
- CPUWriteMemoryFunc * const *mem_write, void *opaque)
-{
- omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
- omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
- omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
-
- return omap_l4_io_entries ++;
-}
-
-static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
-{
- unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
-
- return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
-}
-
-static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
-{
- unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
-
- return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
-}
-
-static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
-{
- unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
-
- return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
-}
-
-static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
-
- return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
-}
-
-static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
-
- return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
-}
-
-static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
-
- return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
-}
-
-static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
- omap_l4_io_readb,
- omap_l4_io_readh,
- omap_l4_io_readw,
-};
-
-static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
- omap_l4_io_writeb,
- omap_l4_io_writeh,
- omap_l4_io_writew,
-};
-#endif
-
-struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
-{
- struct omap_l4_s *bus = qemu_mallocz(
- sizeof(*bus) + ta_num * sizeof(*bus->ta));
-
- bus->ta_num = ta_num;
- bus->base = base;
-
-#ifdef L4_MUX_HACK
- omap_l4_io_entries = 1;
- omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
-
- omap_cpu_io_entry =
- cpu_register_io_memory(omap_l4_io_readfn,
- omap_l4_io_writefn, bus);
-# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
- omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
- omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
- omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
- omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
- omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
- omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
- omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
-#endif
-
- return bus;
-}
-
-static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
-{
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
-
- switch (addr) {
- case 0x00: /* COMPONENT */
- return s->component;
-
- case 0x20: /* AGENT_CONTROL */
- return s->control;
-
- case 0x28: /* AGENT_STATUS */
- return s->status;
- }
-
- OMAP_BAD_REG(addr);
- return 0;
-}
-
-static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
-
- switch (addr) {
- case 0x00: /* COMPONENT */
- case 0x28: /* AGENT_STATUS */
- OMAP_RO_REG(addr);
- break;
-
- case 0x20: /* AGENT_CONTROL */
- s->control = value & 0x01000700;
- if (value & 1) /* OCP_RESET */
- s->status &= ~1; /* REQ_TIMEOUT */
- break;
-
- default:
- OMAP_BAD_REG(addr);
- }
-}
-
-static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
- omap_badwidth_read16,
- omap_l4ta_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_l4ta_write,
-};
-
#define L4TA(n) (n)
#define L4TAO(n) ((n) + 39)
-static struct omap_l4_region_s {
- target_phys_addr_t offset;
- size_t size;
- int access;
-} omap_l4_region[125] = {
+static const struct omap_l4_region_s omap_l4_region[125] = {
[ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
[ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
[ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
[124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
};
-static struct omap_l4_agent_info_s {
- int ta;
- int region;
- int regions;
- int ta_region;
-} omap_l4_agent_info[54] = {
+static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
{ 0, 0, 3, 2 }, /* L4IA initiatior agent */
{ L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
{ L4TAO(2), 5, 2, 1 }, /* 32K timer */
{ L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
};
-#define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
-#define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
-
-struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
-{
- int i, iomemtype;
- struct omap_target_agent_s *ta = NULL;
- struct omap_l4_agent_info_s *info = NULL;
-
- for (i = 0; i < bus->ta_num; i ++)
- if (omap_l4_agent_info[i].ta == cs) {
- ta = &bus->ta[i];
- info = &omap_l4_agent_info[i];
- break;
- }
- if (!ta) {
- fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
- exit(-1);
- }
-
- ta->bus = bus;
- ta->start = &omap_l4_region[info->region];
- ta->regions = info->regions;
-
- ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
- ta->status = 0x00000000;
- ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
-
- iomemtype = l4_register_io_memory(omap_l4ta_readfn,
- omap_l4ta_writefn, ta);
- ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
-
- return ta;
-}
-
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
- int iotype)
-{
- target_phys_addr_t base;
- ssize_t size;
-#ifdef L4_MUX_HACK
- int i;
-#endif
-
- if (region < 0 || region >= ta->regions) {
- fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
- exit(-1);
- }
-
- base = ta->bus->base + ta->start[region].offset;
- size = ta->start[region].size;
- if (iotype) {
-#ifndef L4_MUX_HACK
- cpu_register_physical_memory(base, size, iotype);
-#else
- cpu_register_physical_memory(base, size, omap_cpu_io_entry);
- i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
- for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
- omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
- omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
- omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
- omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
- omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
- omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
- omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
- }
-#endif
- }
-
- return base;
-}
-
-/* TEST-Chip-level TAP */
-static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
-{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
-
- switch (addr) {
- case 0x204: /* IDCODE_reg */
- switch (s->mpu_model) {
- case omap2420:
- case omap2422:
- case omap2423:
- return 0x5b5d902f; /* ES 2.2 */
- case omap2430:
- return 0x5b68a02f; /* ES 2.2 */
- case omap3430:
- return 0x1b7ae02f; /* ES 2 */
- default:
- hw_error("%s: Bad mpu model\n", __FUNCTION__);
- }
-
- case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
- case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
- switch (s->mpu_model) {
- case omap2420:
- return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
- case omap2422:
- return 0x000400f0;
- case omap2423:
- return 0x000800f0;
- case omap2430:
- return 0x000000f0;
- case omap3430:
- return 0x000000f0;
- default:
- hw_error("%s: Bad mpu model\n", __FUNCTION__);
- }
-
- case 0x20c:
- switch (s->mpu_model) {
- case omap2420:
- case omap2422:
- case omap2423:
- return 0xcafeb5d9; /* ES 2.2 */
- case omap2430:
- return 0xcafeb68a; /* ES 2.2 */
- case omap3430:
- return 0xcafeb7ae; /* ES 2 */
- default:
- hw_error("%s: Bad mpu model\n", __FUNCTION__);
- }
-
- case 0x218: /* DIE_ID_reg */
- return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
- case 0x21c: /* DIE_ID_reg */
- return 0x54 << 24;
- case 0x220: /* DIE_ID_reg */
- return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
- case 0x224: /* DIE_ID_reg */
- return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
- }
-
- OMAP_BAD_REG(addr);
- return 0;
-}
-
-static void omap_tap_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- OMAP_BAD_REG(addr);
-}
-
-static CPUReadMemoryFunc * const omap_tap_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_tap_read,
-};
-
-static CPUWriteMemoryFunc * const omap_tap_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_tap_write,
-};
-
-void omap_tap_init(struct omap_target_agent_s *ta,
- struct omap_mpu_state_s *mpu)
-{
- omap_l4_attach(ta, 0, l4_register_io_memory(
- omap_tap_readfn, omap_tap_writefn, mpu));
-}
+#define omap_l4ta(bus, cs) \
+ omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
+#define omap_l4tao(bus, cs) \
+ omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
/* Power, Reset, and Clock Management */
struct omap_prcm_s {
omap_prcm_reset(s);
}
-struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
+static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
struct omap_mpu_state_s *mpu)
{
s->padconf[0x44] = 0x00000800;
}
-struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
+static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu)
{
int iomemtype;
/* Memory-mapped stuff */
cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
- (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
+ (q2_base = qemu_ram_alloc(NULL, "omap2.dram",
+ s->sdram_size)) | IO_MEM_RAM);
cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
- (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
+ (sram_base = qemu_ram_alloc(NULL, "omap2.sram",
+ s->sram_size)) | IO_MEM_RAM);
s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
omap_findclk(s, "uart1_fclk"),
omap_findclk(s, "uart1_iclk"),
s->drq[OMAP24XX_DMA_UART1_TX],
- s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
+ s->drq[OMAP24XX_DMA_UART1_RX],
+ "uart1",
+ serial_hds[0]);
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
s->irq[0][OMAP_INT_24XX_UART2_IRQ],
omap_findclk(s, "uart2_fclk"),
omap_findclk(s, "uart2_iclk"),
s->drq[OMAP24XX_DMA_UART2_TX],
s->drq[OMAP24XX_DMA_UART2_RX],
+ "uart2",
serial_hds[0] ? serial_hds[1] : NULL);
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
s->irq[0][OMAP_INT_24XX_UART3_IRQ],
omap_findclk(s, "uart3_iclk"),
s->drq[OMAP24XX_DMA_UART3_TX],
s->drq[OMAP24XX_DMA_UART3_RX],
+ "uart3",
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
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