#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
-
-/* debug UniNorth */
-//#define DEBUG_UNIN
-
-#ifdef DEBUG_UNIN
-#define UNIN_DPRINTF(fmt, ...) \
- do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define UNIN_DPRINTF(fmt, ...)
-#endif
+#include "hw/pci-host/uninorth.h"
+#include "trace.h"
static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
-#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
-#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
-#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
-#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
-
-#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
-#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
-#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
-#define U3_AGP_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
-
-typedef struct UNINState {
- PCIHostState parent_obj;
-
- MemoryRegion pci_mmio;
- MemoryRegion pci_hole;
-} UNINState;
-
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
- qemu_irq *pic = opaque;
+ UNINHostState *s = opaque;
- UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
- unin_irq_line[irq_num], level);
- qemu_set_irq(pic[unin_irq_line[irq_num]], level);
+ trace_unin_set_irq(unin_irq_line[irq_num], level);
+ qemu_set_irq(s->irqs[irq_num], level);
}
static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
retval |= func << 8;
}
-
- UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
- reg, addr, retval);
+ trace_unin_get_config_reg(reg, addr, retval);
return retval;
}
static void unin_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
- UNINState *s = opaque;
+ UNINHostState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
- UNIN_DPRINTF("write addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
- addr, len, val);
+ trace_unin_data_write(addr, len, val);
pci_data_write(phb->bus,
unin_get_config_reg(phb->config_reg, addr),
val, len);
static uint64_t unin_data_read(void *opaque, hwaddr addr,
unsigned len)
{
- UNINState *s = opaque;
+ UNINHostState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val;
val = pci_data_read(phb->bus,
unin_get_config_reg(phb->config_reg, addr),
len);
- UNIN_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
- addr, len, val);
+ trace_unin_data_read(addr, len, val);
return val;
}
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static int pci_unin_main_init_device(SysBusDevice *dev)
+static void pci_unin_init_irqs(UNINHostState *s)
{
- PCIHostState *h;
+ int i;
- /* Use values found on a real PowerMac */
- /* Uninorth main bus */
- h = PCI_HOST_BRIDGE(dev);
+ for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
+ s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
+ }
+}
- memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
- "pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
+static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev)
+{
+ UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
- return 0;
+ return g_strdup_printf("%x", s->ofw_addr);
}
-
-static int pci_u3_agp_init_device(SysBusDevice *dev)
+static void pci_unin_main_realize(DeviceState *dev, Error **errp)
{
- PCIHostState *h;
+ UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
- /* Uninorth U3 AGP bus */
- h = PCI_HOST_BRIDGE(dev);
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s,
+ &s->pci_mmio,
+ &s->pci_io,
+ PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
- memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
- "pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
+ pci_unin_init_irqs(s);
- return 0;
+ /* DEC 21154 bridge */
+#if 0
+ /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
+ pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
+#endif
}
-static int pci_unin_agp_init_device(SysBusDevice *dev)
+static void pci_unin_main_init(Object *obj)
{
- PCIHostState *h;
-
- /* Uninorth AGP bus */
- h = PCI_HOST_BRIDGE(dev);
+ UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
+ /* Use values found on a real PowerMac */
+ /* Uninorth main bus */
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
- dev, "pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
- return 0;
-}
+ obj, "unin-pci-conf-idx", 0x1000);
+ memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
+ "unin-pci-conf-data", 0x1000);
-static int pci_unin_internal_init_device(SysBusDevice *dev)
-{
- PCIHostState *h;
+ memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
+ 0x100000000ULL);
+ memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
+ "unin-pci-isa-mmio", 0x00800000);
- /* Uninorth internal bus */
- h = PCI_HOST_BRIDGE(dev);
+ memory_region_init_alias(&s->pci_hole, OBJECT(s),
+ "unin-pci-hole", &s->pci_mmio,
+ 0x80000000ULL, 0x10000000ULL);
- memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
- dev, "pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
- return 0;
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
+ sysbus_init_mmio(sbd, &s->pci_hole);
+ sysbus_init_mmio(sbd, &s->pci_io);
}
-PCIBus *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
+static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
{
- DeviceState *dev;
- SysBusDevice *s;
- PCIHostState *h;
- UNINState *d;
+ UNINHostState *s = U3_AGP_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s,
+ &s->pci_mmio,
+ &s->pci_io,
+ PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
+ pci_unin_init_irqs(s);
+}
- /* Use values found on a real PowerMac */
- /* Uninorth main bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- h = PCI_HOST_BRIDGE(s);
- d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
- memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
- memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
- 0x80000000ULL, 0x10000000ULL);
- memory_region_add_subregion(address_space_mem, 0x80000000ULL,
- &d->pci_hole);
+static void pci_u3_agp_init(Object *obj)
+{
+ UNINHostState *s = U3_AGP_HOST_BRIDGE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
- h->bus = pci_register_bus(dev, NULL,
- pci_unin_set_irq, pci_unin_map_irq,
- pic,
- &d->pci_mmio,
- address_space_io,
- PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+ /* Uninorth U3 AGP bus */
+ memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
+ obj, "unin-pci-conf-idx", 0x1000);
+ memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
+ "unin-pci-conf-data", 0x1000);
-#if 0
- pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
-#endif
+ memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
+ 0x100000000ULL);
+ memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
+ "unin-pci-isa-mmio", 0x00800000);
- sysbus_mmio_map(s, 0, 0xf2800000);
- sysbus_mmio_map(s, 1, 0xf2c00000);
+ memory_region_init_alias(&s->pci_hole, OBJECT(s),
+ "unin-pci-hole", &s->pci_mmio,
+ 0x80000000ULL, 0x70000000ULL);
- /* DEC 21154 bridge */
-#if 0
- /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
- pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
-#endif
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
- /* Uninorth AGP bus */
- pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
- dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(s, 0, 0xf0800000);
- sysbus_mmio_map(s, 1, 0xf0c00000);
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
+ sysbus_init_mmio(sbd, &s->pci_hole);
+ sysbus_init_mmio(sbd, &s->pci_io);
+}
- /* Uninorth internal bus */
-#if 0
- /* XXX: not needed for now */
- pci_create_simple(h->bus, PCI_DEVFN(14, 0),
- "uni-north-internal-pci");
- dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(s, 0, 0xf4800000);
- sysbus_mmio_map(s, 1, 0xf4c00000);
-#endif
+static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
+{
+ UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s,
+ &s->pci_mmio,
+ &s->pci_io,
+ PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
- return h->bus;
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
+ pci_unin_init_irqs(s);
}
-PCIBus *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
+static void pci_unin_agp_init(Object *obj)
{
- DeviceState *dev;
- SysBusDevice *s;
- PCIHostState *h;
- UNINState *d;
+ UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Uninorth AGP bus */
+ memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
+ obj, "unin-agp-conf-idx", 0x1000);
+ memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
+ obj, "unin-agp-conf-data", 0x1000);
- dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- h = PCI_HOST_BRIDGE(dev);
- d = U3_AGP_HOST_BRIDGE(dev);
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
- memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
- memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
- 0x80000000ULL, 0x70000000ULL);
- memory_region_add_subregion(address_space_mem, 0x80000000ULL,
- &d->pci_hole);
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
+}
- h->bus = pci_register_bus(dev, NULL,
- pci_unin_set_irq, pci_unin_map_irq,
- pic,
- &d->pci_mmio,
- address_space_io,
- PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
+{
+ UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s,
+ &s->pci_mmio,
+ &s->pci_io,
+ PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
+
+ pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
+ pci_unin_init_irqs(s);
+}
- sysbus_mmio_map(s, 0, 0xf0800000);
- sysbus_mmio_map(s, 1, 0xf0c00000);
+static void pci_unin_internal_init(Object *obj)
+{
+ UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
- pci_create_simple(h->bus, 11 << 3, "u3-agp");
+ /* Uninorth internal bus */
+ memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
+ obj, "unin-pci-conf-idx", 0x1000);
+ memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
+ obj, "unin-pci-conf-data", 0x1000);
- return h->bus;
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
}
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x10; // latency_timer
- d->config[0x34] = 0x00; // capabilities_pointer
-}
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer */
+ d->config[0x34] = 0x00;
-static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
-{
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x10; // latency_timer
- // d->config[0x34] = 0x80; // capabilities_pointer
/*
* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
* memory space with base 0x80000000, size 0x10000000 for Apple's
d->config[0x4b] = 0x1;
}
+static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
+{
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer
+ d->config[0x34] = 0x80; */
+}
+
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
/* cache line size */
static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x10; // latency_timer
- d->config[0x34] = 0x00; // capabilities_pointer
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer */
+ d->config[0x34] = 0x00;
}
static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = unin_main_pci_host_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
};
static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = u3_agp_pci_host_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
};
static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = unin_agp_pci_host_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
};
static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = unin_internal_pci_host_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+static Property pci_unin_main_pci_host_props[] = {
+ DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1),
+ DEFINE_PROP_END_OF_LIST()
};
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
- sbc->init = pci_unin_main_init_device;
+ dc->realize = pci_unin_main_realize;
+ dc->props = pci_unin_main_pci_host_props;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->fw_name = "pci";
+ sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address;
}
static const TypeInfo pci_unin_main_info = {
.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
+ .instance_init = pci_unin_main_init,
.class_init = pci_unin_main_class_init,
};
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_u3_agp_init_device;
+ dc->realize = pci_u3_agp_realize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
static const TypeInfo pci_u3_agp_info = {
.name = TYPE_U3_AGP_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
+ .instance_init = pci_u3_agp_init,
.class_init = pci_u3_agp_class_init,
};
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_unin_agp_init_device;
+ dc->realize = pci_unin_agp_realize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
static const TypeInfo pci_unin_agp_info = {
.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
+ .instance_init = pci_unin_agp_init,
.class_init = pci_unin_agp_class_init,
};
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_unin_internal_init_device;
+ dc->realize = pci_unin_internal_realize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
static const TypeInfo pci_unin_internal_info = {
.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
+ .instance_init = pci_unin_internal_init,
.class_init = pci_unin_internal_class_init,
};
+/* UniN device */
+static void unin_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ trace_unin_write(addr, value);
+}
+
+static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
+{
+ uint32_t value;
+
+ switch (addr) {
+ case 0:
+ value = UNINORTH_VERSION_10A;
+ break;
+ default:
+ value = 0;
+ }
+
+ trace_unin_read(addr, value);
+
+ return value;
+}
+
+static const MemoryRegionOps unin_ops = {
+ .read = unin_read,
+ .write = unin_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void unin_init(Object *obj)
+{
+ UNINState *s = UNI_NORTH(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000);
+
+ sysbus_init_mmio(sbd, &s->mem);
+}
+
+static void unin_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+}
+
+static const TypeInfo unin_info = {
+ .name = TYPE_UNI_NORTH,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(UNINState),
+ .instance_init = unin_init,
+ .class_init = unin_class_init,
+};
+
static void unin_register_types(void)
{
type_register_static(&unin_main_pci_host_info);
type_register_static(&pci_u3_agp_info);
type_register_static(&pci_unin_agp_info);
type_register_static(&pci_unin_internal_info);
+
+ type_register_static(&unin_info);
}
type_init(unin_register_types)
projects / qemu.git / blobdiff