#include "hw/acpi/tpm.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-host/gpex.h"
#include "hw/arm/virt.h"
#include "hw/mem/nvdimm.h"
#include "hw/platform-bus.h"
#include "kvm_arm.h"
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
+#include "hw/acpi/viot.h"
#define ARM_SPI_BASE 32
-static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
+#define ACPI_BUILD_TABLE_SIZE 0x20000
+
+static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
{
+ MachineState *ms = MACHINE(vms);
uint16_t i;
- for (i = 0; i < smp_cpus; i++) {
+ for (i = 0; i < ms->smp.cpus; i++) {
Aml *dev = aml_device("C%.03X", i);
aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
aml_append(dev, aml_name_decl("_UID", aml_int(i)));
}
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
- uint32_t irq, bool use_highmem, bool highmem_ecam)
+ uint32_t irq, VirtMachineState *vms)
{
- int ecam_id = VIRT_ECAM_ID(highmem_ecam);
- Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
- int i, slot_no;
- hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
- hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
- hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
- hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
- hwaddr base_ecam = memmap[ecam_id].base;
- hwaddr size_ecam = memmap[ecam_id].size;
- int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
-
- Aml *dev = aml_device("%s", "PCI0");
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
- aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
- aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
- aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
- aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
- aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
- aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+ int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
+ struct GPEXConfig cfg = {
+ .mmio32 = memmap[VIRT_PCIE_MMIO],
+ .pio = memmap[VIRT_PCIE_PIO],
+ .ecam = memmap[ecam_id],
+ .irq = irq,
+ .bus = vms->bus,
+ };
- /* Declare the PCI Routing Table. */
- Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
- for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
- for (i = 0; i < PCI_NUM_PINS; i++) {
- int gsi = (i + slot_no) % PCI_NUM_PINS;
- Aml *pkg = aml_package(4);
- aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
- aml_append(pkg, aml_int(i));
- aml_append(pkg, aml_name("GSI%d", gsi));
- aml_append(pkg, aml_int(0));
- aml_append(rt_pkg, pkg);
- }
+ if (vms->highmem_mmio) {
+ cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
}
- aml_append(dev, aml_name_decl("_PRT", rt_pkg));
-
- /* Create GSI link device */
- for (i = 0; i < PCI_NUM_PINS; i++) {
- uint32_t irqs = irq + i;
- Aml *dev_gsi = aml_device("GSI%d", i);
- aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
- aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
- crs = aml_resource_template();
- aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, &irqs, 1));
- aml_append(dev_gsi, aml_name_decl("_PRS", crs));
- crs = aml_resource_template();
- aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, &irqs, 1));
- aml_append(dev_gsi, aml_name_decl("_CRS", crs));
- method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
- aml_append(dev_gsi, method);
- aml_append(dev, dev_gsi);
- }
-
- method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_int(base_ecam)));
- aml_append(dev, method);
-
- method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
- Aml *rbuf = aml_resource_template();
- aml_append(rbuf,
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
- nr_pcie_buses));
- aml_append(rbuf,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
- base_mmio + size_mmio - 1, 0x0000, size_mmio));
- aml_append(rbuf,
- aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
- size_pio));
-
- if (use_highmem) {
- hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
- hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
-
- aml_append(rbuf,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- base_mmio_high,
- base_mmio_high + size_mmio_high - 1, 0x0000,
- size_mmio_high));
- }
-
- aml_append(method, aml_return(rbuf));
- aml_append(dev, method);
-
- /* Declare an _OSC (OS Control Handoff) method */
- aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
- aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
- method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
- aml_append(method,
- aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
-
- /* PCI Firmware Specification 3.0
- * 4.5.1. _OSC Interface for PCI Host Bridge Devices
- * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
- * identified by the Universal Unique IDentifier (UUID)
- * 33DB4D5B-1FF7-401C-9657-7441C03DD766
- */
- UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
- ifctx = aml_if(aml_equal(aml_arg(0), UUID));
- aml_append(ifctx,
- aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
- aml_append(ifctx,
- aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
- aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
- aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
- /*
- * Allow OS control for all 5 features:
- * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
- */
- aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
- aml_name("CTRL")));
-
- ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
- aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
- aml_name("CDW1")));
- aml_append(ifctx, ifctx1);
-
- ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
- aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
- aml_name("CDW1")));
- aml_append(ifctx, ifctx1);
-
- aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
- aml_append(ifctx, aml_return(aml_arg(3)));
- aml_append(method, ifctx);
-
- elsectx = aml_else();
- aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
- aml_name("CDW1")));
- aml_append(elsectx, aml_return(aml_arg(3)));
- aml_append(method, elsectx);
- aml_append(dev, method);
-
- method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
-
- /* PCI Firmware Specification 3.0
- * 4.6.1. _DSM for PCI Express Slot Information
- * The UUID in _DSM in this context is
- * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
- */
- UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
- ifctx = aml_if(aml_equal(aml_arg(0), UUID));
- ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
- uint8_t byte_list[1] = {1};
- buf = aml_buffer(1, byte_list);
- aml_append(ifctx1, aml_return(buf));
- aml_append(ifctx, ifctx1);
- aml_append(method, ifctx);
-
- byte_list[0] = 0;
- buf = aml_buffer(1, byte_list);
- aml_append(method, aml_return(buf));
- aml_append(dev, method);
-
- Aml *dev_res0 = aml_device("%s", "RES0");
- aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
- crs = aml_resource_template();
- aml_append(crs,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
- base_ecam + size_ecam - 1, 0x0000, size_ecam));
- aml_append(dev_res0, aml_name_decl("_CRS", crs));
- aml_append(dev, dev_res0);
- aml_append(scope, dev);
+ acpi_dsdt_add_gpex(scope, &cfg);
}
static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
aml_append(scope, dev);
}
-static void acpi_dsdt_add_power_button(Aml *scope)
-{
- Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
- aml_append(dev, aml_name_decl("_UID", aml_int(0)));
- aml_append(scope, dev);
-}
-
+#ifdef CONFIG_TPM
static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
{
PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
Aml *dev = aml_device("TPM0");
aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+ aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
Aml *crs = aml_resource_template();
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
}
+#endif
+
+#define ID_MAPPING_ENTRY_SIZE 20
+#define SMMU_V3_ENTRY_SIZE 68
+#define ROOT_COMPLEX_ENTRY_SIZE 36
+#define IORT_NODE_OFFSET 48
+
+static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
+ uint32_t id_count, uint32_t out_ref)
+{
+ /* Table 4 ID mapping format */
+ build_append_int_noprefix(table_data, input_base, 4); /* Input base */
+ build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */
+ build_append_int_noprefix(table_data, input_base, 4); /* Output base */
+ build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
+ /* Flags */
+ build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4);
+}
+
+struct AcpiIortIdMapping {
+ uint32_t input_base;
+ uint32_t id_count;
+};
+typedef struct AcpiIortIdMapping AcpiIortIdMapping;
+
+/* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
+static int
+iort_host_bridges(Object *obj, void *opaque)
+{
+ GArray *idmap_blob = opaque;
+
+ if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
+ PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
+
+ if (bus && !pci_bus_bypass_iommu(bus)) {
+ int min_bus, max_bus;
+
+ pci_bus_range(bus, &min_bus, &max_bus);
+
+ AcpiIortIdMapping idmap = {
+ .input_base = min_bus << 8,
+ .id_count = (max_bus - min_bus + 1) << 8,
+ };
+ g_array_append_val(idmap_blob, idmap);
+ }
+ }
+
+ return 0;
+}
+
+static int iort_idmap_compare(gconstpointer a, gconstpointer b)
+{
+ AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
+ AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
+
+ return idmap_a->input_base - idmap_b->input_base;
+}
+/*
+ * Input Output Remapping Table (IORT)
+ * Conforms to "IO Remapping Table System Software on ARM Platforms",
+ * Document number: ARM DEN 0049E.b, Feb 2021
+ */
static void
build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- int nb_nodes, iort_start = table_data->len;
+ int i, nb_nodes, rc_mapping_count;
+ const uint32_t iort_node_offset = IORT_NODE_OFFSET;
+ size_t node_size, smmu_offset = 0;
AcpiIortIdMapping *idmap;
- AcpiIortItsGroup *its;
- AcpiIortTable *iort;
- AcpiIortSmmu3 *smmu;
- size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
- AcpiIortRC *rc;
+ uint32_t id = 0;
+ GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
+ GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
- iort = acpi_data_push(table_data, sizeof(*iort));
+ AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+ /* Table 2 The IORT */
+ acpi_table_begin(&table, table_data);
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
+ AcpiIortIdMapping next_range = {0};
+
+ object_child_foreach_recursive(object_get_root(),
+ iort_host_bridges, smmu_idmaps);
+
+ /* Sort the smmu idmap by input_base */
+ g_array_sort(smmu_idmaps, iort_idmap_compare);
+
+ /*
+ * Split the whole RIDs by mapping from RC to SMMU,
+ * build the ID mapping from RC to ITS directly.
+ */
+ for (i = 0; i < smmu_idmaps->len; i++) {
+ idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
+
+ if (next_range.input_base < idmap->input_base) {
+ next_range.id_count = idmap->input_base - next_range.input_base;
+ g_array_append_val(its_idmaps, next_range);
+ }
+
+ next_range.input_base = idmap->input_base + idmap->id_count;
+ }
+
+ /* Append the last RC -> ITS ID mapping */
+ if (next_range.input_base < 0xFFFF) {
+ next_range.id_count = 0xFFFF - next_range.input_base;
+ g_array_append_val(its_idmaps, next_range);
+ }
+
nb_nodes = 3; /* RC, ITS, SMMUv3 */
+ rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
} else {
nb_nodes = 2; /* RC, ITS */
+ rc_mapping_count = 1;
}
-
- iort_length = sizeof(*iort);
- iort->node_count = cpu_to_le32(nb_nodes);
- /*
- * Use a copy in case table_data->data moves during acpi_data_push
- * operations.
- */
- iort_node_offset = sizeof(*iort);
- iort->node_offset = cpu_to_le32(iort_node_offset);
-
- /* ITS group node */
- node_size = sizeof(*its) + sizeof(uint32_t);
- iort_length += node_size;
- its = acpi_data_push(table_data, node_size);
-
- its->type = ACPI_IORT_NODE_ITS_GROUP;
- its->length = cpu_to_le16(node_size);
- its->its_count = cpu_to_le32(1);
- its->identifiers[0] = 0; /* MADT translation_id */
+ /* Number of IORT Nodes */
+ build_append_int_noprefix(table_data, nb_nodes, 4);
+
+ /* Offset to Array of IORT Nodes */
+ build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+
+ /* Table 12 ITS Group Format */
+ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
+ node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
+ build_append_int_noprefix(table_data, node_size, 2); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Revision */
+ build_append_int_noprefix(table_data, id++, 4); /* Identifier */
+ build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
+ build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
+ build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
+ /* GIC ITS Identifier Array */
+ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
- /* SMMUv3 node */
- smmu_offset = iort_node_offset + node_size;
- node_size = sizeof(*smmu) + sizeof(*idmap);
- iort_length += node_size;
- smmu = acpi_data_push(table_data, node_size);
-
- smmu->type = ACPI_IORT_NODE_SMMU_V3;
- smmu->length = cpu_to_le16(node_size);
- smmu->mapping_count = cpu_to_le32(1);
- smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
- smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
- smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
- smmu->event_gsiv = cpu_to_le32(irq);
- smmu->pri_gsiv = cpu_to_le32(irq + 1);
- smmu->gerr_gsiv = cpu_to_le32(irq + 2);
- smmu->sync_gsiv = cpu_to_le32(irq + 3);
-
- /* Identity RID mapping covering the whole input RID range */
- idmap = &smmu->id_mapping_array[0];
- idmap->input_base = 0;
- idmap->id_count = cpu_to_le32(0xFFFF);
- idmap->output_base = 0;
+ smmu_offset = table_data->len - table.table_offset;
+ /* Table 9 SMMUv3 Format */
+ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
+ node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
+ build_append_int_noprefix(table_data, node_size, 2); /* Length */
+ build_append_int_noprefix(table_data, 4, 1); /* Revision */
+ build_append_int_noprefix(table_data, id++, 4); /* Identifier */
+ build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
+ /* Reference to ID Array */
+ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
+ /* Base address */
+ build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
+ /* Flags */
+ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
+ /* Model */
+ build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
+ build_append_int_noprefix(table_data, irq, 4); /* Event */
+ build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
+ build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
+ build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
+ build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
+ /* DeviceID mapping index (ignored since interrupts are GSIV based) */
+ build_append_int_noprefix(table_data, 0, 4);
+
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort_node_offset);
+ build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
}
- /* Root Complex Node */
- node_size = sizeof(*rc) + sizeof(*idmap);
- iort_length += node_size;
- rc = acpi_data_push(table_data, node_size);
-
- rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
- rc->length = cpu_to_le16(node_size);
- rc->mapping_count = cpu_to_le32(1);
- rc->mapping_offset = cpu_to_le32(sizeof(*rc));
-
- /* fully coherent device */
- rc->memory_properties.cache_coherency = cpu_to_le32(1);
- rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
- rc->pci_segment_number = 0; /* MCFG pci_segment */
-
- /* Identity RID mapping covering the whole input RID range */
- idmap = &rc->id_mapping_array[0];
- idmap->input_base = 0;
- idmap->id_count = cpu_to_le32(0xFFFF);
- idmap->output_base = 0;
-
+ /* Table 17 Root Complex Node */
+ build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
+ node_size = ROOT_COMPLEX_ENTRY_SIZE +
+ ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
+ build_append_int_noprefix(table_data, node_size, 2); /* Length */
+ build_append_int_noprefix(table_data, 3, 1); /* Revision */
+ build_append_int_noprefix(table_data, id++, 4); /* Identifier */
+ /* Number of ID mappings */
+ build_append_int_noprefix(table_data, rc_mapping_count, 4);
+ /* Reference to ID Array */
+ build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
+
+ /* Table 14 Memory access properties */
+ /* CCA: Cache Coherent Attribute */
+ build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
+ build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* Table 15 Memory Access Flags */
+ build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
+
+ build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
+ /* MCFG pci_segment */
+ build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
+
+ /* Memory address size limit */
+ build_append_int_noprefix(table_data, 64, 1);
+
+ build_append_int_noprefix(table_data, 0, 3); /* Reserved */
+
+ /* Output Reference */
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
- /* output IORT node is the smmuv3 node */
- idmap->output_reference = cpu_to_le32(smmu_offset);
+ AcpiIortIdMapping *range;
+
+ /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
+ for (i = 0; i < smmu_idmaps->len; i++) {
+ range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
+ /* output IORT node is the smmuv3 node */
+ build_iort_id_mapping(table_data, range->input_base,
+ range->id_count, smmu_offset);
+ }
+
+ /* bypassed RIDs connect to ITS group node directly: RC -> ITS */
+ for (i = 0; i < its_idmaps->len; i++) {
+ range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
+ /* output IORT node is the ITS group node (the first node) */
+ build_iort_id_mapping(table_data, range->input_base,
+ range->id_count, iort_node_offset);
+ }
} else {
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort_node_offset);
+ build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
}
- /*
- * Update the pointer address in case table_data->data moves during above
- * acpi_data_push operations.
- */
- iort = (AcpiIortTable *)(table_data->data + iort_start);
- iort->length = cpu_to_le32(iort_length);
-
- build_header(linker, table_data, (void *)(table_data->data + iort_start),
- "IORT", table_data->len - iort_start, 0, NULL, NULL);
+ acpi_table_end(linker, &table);
+ g_array_free(smmu_idmaps, true);
+ g_array_free(its_idmaps, true);
}
+/*
+ * Serial Port Console Redirection Table (SPCR)
+ * Rev: 1.07
+ */
static void
build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- AcpiSerialPortConsoleRedirection *spcr;
- const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
- int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
- int spcr_start = table_data->len;
-
- spcr = acpi_data_push(table_data, sizeof(*spcr));
-
- spcr->interface_type = 0x3; /* ARM PL011 UART */
-
- spcr->base_address.space_id = AML_SYSTEM_MEMORY;
- spcr->base_address.bit_width = 8;
- spcr->base_address.bit_offset = 0;
- spcr->base_address.access_width = 1;
- spcr->base_address.address = cpu_to_le64(uart_memmap->base);
-
- spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
- spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
-
- spcr->baud = 3; /* Baud Rate: 3 = 9600 */
- spcr->parity = 0; /* No Parity */
- spcr->stopbits = 1; /* 1 Stop bit */
- spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
- spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
-
- spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
- spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
-
- build_header(linker, table_data, (void *)(table_data->data + spcr_start),
- "SPCR", table_data->len - spcr_start, 2, NULL, NULL);
+ AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
+ /* Interface Type */
+ build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
+ build_append_int_noprefix(table_data, 0, 3); /* Reserved */
+ /* Base Address */
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
+ vms->memmap[VIRT_UART].base);
+ /* Interrupt Type */
+ build_append_int_noprefix(table_data,
+ (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
+ build_append_int_noprefix(table_data, 0, 1); /* IRQ */
+ /* Global System Interrupt */
+ build_append_int_noprefix(table_data,
+ vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
+ build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
+ build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */
+ /* Stop Bits */
+ build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1);
+ /* Flow Control */
+ build_append_int_noprefix(table_data,
+ (1 << 1) /* RTS/CTS hardware flow control */, 1);
+ /* Terminal Type */
+ build_append_int_noprefix(table_data, 0 /* VT100 */, 1);
+ build_append_int_noprefix(table_data, 0, 1); /* Language */
+ /* PCI Device ID */
+ build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
+ /* PCI Vendor ID */
+ build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */
+ build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+
+ acpi_table_end(linker, &table);
}
+/*
+ * ACPI spec, Revision 5.1
+ * 5.2.16 System Resource Affinity Table (SRAT)
+ */
static void
build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- AcpiSystemResourceAffinityTable *srat;
- AcpiSratProcessorGiccAffinity *core;
- AcpiSratMemoryAffinity *numamem;
- int i, srat_start;
+ int i;
uint64_t mem_base;
MachineClass *mc = MACHINE_GET_CLASS(vms);
MachineState *ms = MACHINE(vms);
const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
+ AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
- srat_start = table_data->len;
- srat = acpi_data_push(table_data, sizeof(*srat));
- srat->reserved1 = cpu_to_le32(1);
+ acpi_table_begin(&table, table_data);
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
for (i = 0; i < cpu_list->len; ++i) {
- core = acpi_data_push(table_data, sizeof(*core));
- core->type = ACPI_SRAT_PROCESSOR_GICC;
- core->length = sizeof(*core);
- core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
- core->acpi_processor_uid = cpu_to_le32(i);
- core->flags = cpu_to_le32(1);
+ uint32_t nodeid = cpu_list->cpus[i].props.node_id;
+ /*
+ * 5.2.16.4 GICC Affinity Structure
+ */
+ build_append_int_noprefix(table_data, 3, 1); /* Type */
+ build_append_int_noprefix(table_data, 18, 1); /* Length */
+ build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+ /* Flags, Table 5-76 */
+ build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
}
mem_base = vms->memmap[VIRT_MEM].base;
for (i = 0; i < ms->numa_state->num_nodes; ++i) {
if (ms->numa_state->nodes[i].node_mem > 0) {
- numamem = acpi_data_push(table_data, sizeof(*numamem));
- build_srat_memory(numamem, mem_base,
+ build_srat_memory(table_data, mem_base,
ms->numa_state->nodes[i].node_mem, i,
MEM_AFFINITY_ENABLED);
mem_base += ms->numa_state->nodes[i].node_mem;
}
if (ms->device_memory) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, ms->device_memory->base,
+ build_srat_memory(table_data, ms->device_memory->base,
memory_region_size(&ms->device_memory->mr),
ms->numa_state->num_nodes - 1,
MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
}
- build_header(linker, table_data, (void *)(table_data->data + srat_start),
- "SRAT", table_data->len - srat_start, 3, NULL, NULL);
+ acpi_table_end(linker, &table);
}
-/* GTDT */
+/*
+ * ACPI spec, Revision 5.1
+ * 5.2.24 Generic Timer Description Table (GTDT)
+ */
static void
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
- int gtdt_start = table_data->len;
- AcpiGenericTimerTable *gtdt;
- uint32_t irqflags;
-
- if (vmc->claim_edge_triggered_timers) {
- irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
- } else {
- irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
- }
-
- gtdt = acpi_data_push(table_data, sizeof *gtdt);
- /* The interrupt values are the same with the device tree when adding 16 */
- gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
- gtdt->secure_el1_flags = cpu_to_le32(irqflags);
-
- gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
- gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
- ACPI_GTDT_CAP_ALWAYS_ON);
-
- gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
- gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
+ /*
+ * Table 5-117 Flag Definitions
+ * set only "Timer interrupt Mode" and assume "Timer Interrupt
+ * polarity" bit as '0: Interrupt is Active high'
+ */
+ uint32_t irqflags = vmc->claim_edge_triggered_timers ?
+ 1 : /* Interrupt is Edge triggered */
+ 0; /* Interrupt is Level triggered */
+ AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
+ /* CntControlBase Physical Address */
+ /* FIXME: invalid value, should be 0xFFFFFFFFFFFFFFFF if not impl. ? */
+ build_append_int_noprefix(table_data, 0, 8);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ /*
+ * FIXME: clarify comment:
+ * The interrupt values are the same with the device tree when adding 16
+ */
+ /* Secure EL1 timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
+ /* Secure EL1 timer Flags */
+ build_append_int_noprefix(table_data, irqflags, 4);
+ /* Non-Secure EL1 timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
+ /* Non-Secure EL1 timer Flags */
+ build_append_int_noprefix(table_data, irqflags |
+ 1UL << 2, /* Always-on Capability */
+ 4);
+ /* Virtual timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
+ /* Virtual Timer Flags */
+ build_append_int_noprefix(table_data, irqflags, 4);
+ /* Non-Secure EL2 timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
+ /* Non-Secure EL2 timer Flags */
+ build_append_int_noprefix(table_data, irqflags, 4);
+ /* CntReadBase Physical address */
+ build_append_int_noprefix(table_data, 0, 8);
+ /* Platform Timer Count */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Platform Timer Offset */
+ build_append_int_noprefix(table_data, 0, 4);
+
+ acpi_table_end(linker, &table);
+}
- gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
- gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
+/* Debug Port Table 2 (DBG2) */
+static void
+build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+{
+ AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+ int dbg2devicelength;
+ const char name[] = "COM0";
+ const int namespace_length = sizeof(name);
+
+ acpi_table_begin(&table, table_data);
+
+ dbg2devicelength = 22 + /* BaseAddressRegister[] offset */
+ 12 + /* BaseAddressRegister[] */
+ 4 + /* AddressSize[] */
+ namespace_length /* NamespaceString[] */;
+
+ /* OffsetDbgDeviceInfo */
+ build_append_int_noprefix(table_data, 44, 4);
+ /* NumberDbgDeviceInfo */
+ build_append_int_noprefix(table_data, 1, 4);
+
+ /* Table 2. Debug Device Information structure format */
+ build_append_int_noprefix(table_data, 0, 1); /* Revision */
+ build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */
+ /* NumberofGenericAddressRegisters */
+ build_append_int_noprefix(table_data, 1, 1);
+ /* NameSpaceStringLength */
+ build_append_int_noprefix(table_data, namespace_length, 2);
+ build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */
+ build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */
+ /* OemDataOffset (0 means no OEM data) */
+ build_append_int_noprefix(table_data, 0, 2);
+
+ /* Port Type */
+ build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2);
+ /* Port Subtype */
+ build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2);
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* BaseAddressRegisterOffset */
+ build_append_int_noprefix(table_data, 22, 2);
+ /* AddressSizeOffset */
+ build_append_int_noprefix(table_data, 34, 2);
+
+ /* BaseAddressRegister[] */
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
+ vms->memmap[VIRT_UART].base);
+
+ /* AddressSize[] */
+ build_append_int_noprefix(table_data,
+ vms->memmap[VIRT_UART].size, 4);
+
+ /* NamespaceString[] */
+ g_array_append_vals(table_data, name, namespace_length);
+
+ acpi_table_end(linker, &table);
+};
- build_header(linker, table_data,
- (void *)(table_data->data + gtdt_start), "GTDT",
- table_data->len - gtdt_start, 2, NULL, NULL);
+/*
+ * ACPI spec, Revision 5.1 Errata A
+ * 5.2.12 Multiple APIC Description Table (MADT)
+ */
+static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
+{
+ build_append_int_noprefix(table_data, 0xE, 1); /* Type */
+ build_append_int_noprefix(table_data, 16, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* Discovery Range Base Addres */
+ build_append_int_noprefix(table_data, base, 8);
+ build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
}
-/* MADT */
static void
build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
+ int i;
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
- int madt_start = table_data->len;
const MemMapEntry *memmap = vms->memmap;
- const int *irqmap = vms->irqmap;
- AcpiMultipleApicTable *madt;
- AcpiMadtGenericDistributor *gicd;
- AcpiMadtGenericMsiFrame *gic_msi;
- int i;
-
- madt = acpi_data_push(table_data, sizeof *madt);
-
- gicd = acpi_data_push(table_data, sizeof *gicd);
- gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
- gicd->length = sizeof(*gicd);
- gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
- gicd->version = vms->gic_version;
-
- for (i = 0; i < vms->smp_cpus; i++) {
- AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
- sizeof(*gicc));
+ AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+ /* Local Interrupt Controller Address */
+ build_append_int_noprefix(table_data, 0, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+
+ /* 5.2.12.15 GIC Distributor Structure */
+ build_append_int_noprefix(table_data, 0xC, 1); /* Type */
+ build_append_int_noprefix(table_data, 24, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* GIC ID */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
+ build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */
+ /* GIC version */
+ build_append_int_noprefix(table_data, vms->gic_version, 1);
+ build_append_int_noprefix(table_data, 0, 3); /* Reserved */
+
+ for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
-
- gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
- gicc->length = sizeof(*gicc);
- if (vms->gic_version == 2) {
- gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
- gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
- gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
+ uint64_t physical_base_address = 0, gich = 0, gicv = 0;
+ uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
+ uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
+ PPI(VIRTUAL_PMU_IRQ) : 0;
+
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
+ physical_base_address = memmap[VIRT_GIC_CPU].base;
+ gicv = memmap[VIRT_GIC_VCPU].base;
+ gich = memmap[VIRT_GIC_HYP].base;
}
- gicc->cpu_interface_number = cpu_to_le32(i);
- gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
- gicc->uid = cpu_to_le32(i);
- gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
- if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
- gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
- }
- if (vms->virt) {
- gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
- }
+ /* 5.2.12.14 GIC Structure */
+ build_append_int_noprefix(table_data, 0xB, 1); /* Type */
+ build_append_int_noprefix(table_data, 76, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, i, 4); /* GIC ID */
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+ /* Flags */
+ build_append_int_noprefix(table_data, 1, 4); /* Enabled */
+ /* Parking Protocol Version */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Performance Interrupt GSIV */
+ build_append_int_noprefix(table_data, pmu_interrupt, 4);
+ build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, physical_base_address, 8);
+ build_append_int_noprefix(table_data, gicv, 8); /* GICV */
+ build_append_int_noprefix(table_data, gich, 8); /* GICH */
+ /* VGIC Maintenance interrupt */
+ build_append_int_noprefix(table_data, vgic_interrupt, 4);
+ build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
+ /* MPIDR */
+ build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
}
- if (vms->gic_version == 3) {
- AcpiMadtGenericTranslator *gic_its;
- int nb_redist_regions = virt_gicv3_redist_region_count(vms);
- AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
- sizeof *gicr);
-
- gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
- gicr->length = sizeof(*gicr);
- gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
- gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
-
- if (nb_redist_regions == 2) {
- gicr = acpi_data_push(table_data, sizeof(*gicr));
- gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
- gicr->length = sizeof(*gicr);
- gicr->base_address =
- cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
- gicr->range_length =
- cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
+ if (vms->gic_version != VIRT_GIC_VERSION_2) {
+ build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
+ memmap[VIRT_GIC_REDIST].size);
+ if (virt_gicv3_redist_region_count(vms) == 2) {
+ build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
+ memmap[VIRT_HIGH_GIC_REDIST2].size);
}
if (its_class_name() && !vmc->no_its) {
- gic_its = acpi_data_push(table_data, sizeof *gic_its);
- gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
- gic_its->length = sizeof(*gic_its);
- gic_its->translation_id = 0;
- gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
+ /*
+ * FIXME: Structure is from Revision 6.0 where 'GIC Structure'
+ * has additional fields on top of implemented 5.1 Errata A,
+ * to make it consistent with v6.0 we need to bump everything
+ * to v6.0
+ */
+ /*
+ * ACPI spec, Revision 6.0 Errata A
+ * (original 6.0 definition has invalid Length)
+ * 5.2.12.18 GIC ITS Structure
+ */
+ build_append_int_noprefix(table_data, 0xF, 1); /* Type */
+ build_append_int_noprefix(table_data, 20, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
}
} else {
- gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
- gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
- gic_msi->length = sizeof(*gic_msi);
- gic_msi->gic_msi_frame_id = 0;
- gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
- gic_msi->flags = cpu_to_le32(1);
- gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
- gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
- }
-
- build_header(linker, table_data,
- (void *)(table_data->data + madt_start), "APIC",
- table_data->len - madt_start, 3, NULL, NULL);
+ const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
+
+ /* 5.2.12.16 GIC MSI Frame Structure */
+ build_append_int_noprefix(table_data, 0xD, 1); /* Type */
+ build_append_int_noprefix(table_data, 24, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
+ build_append_int_noprefix(table_data, 1, 4); /* Flags */
+ /* SPI Count */
+ build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
+ build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
+ }
+ acpi_table_end(linker, &table);
}
/* FADT */
g_assert_not_reached();
}
- build_fadt(table_data, linker, &fadt, NULL, NULL);
+ build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
}
/* DSDT */
MachineState *ms = MACHINE(vms);
const MemMapEntry *memmap = vms->memmap;
const int *irqmap = vms->irqmap;
+ AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+ acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
- /* Reserve space for header */
- acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
/* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
* While UEFI can use libfdt to disable the RTC device node in the DTB that
* the RTC ACPI device at all when using UEFI.
*/
scope = aml_scope("\\_SB");
- acpi_dsdt_add_cpus(scope, vms->smp_cpus);
+ acpi_dsdt_add_cpus(scope, vms);
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
(irqmap[VIRT_UART] + ARM_SPI_BASE));
if (vmc->acpi_expose_flash) {
acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
- acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
- vms->highmem, vms->highmem_ecam);
+ acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
HOTPLUG_HANDLER(vms->acpi_dev),
}
acpi_dsdt_add_power_button(scope);
+#ifdef CONFIG_TPM
acpi_dsdt_add_tpm(scope, vms);
+#endif
aml_append(dsdt, scope);
- /* copy AML table into ACPI tables blob and patch header there */
+ /* copy AML table into ACPI tables blob */
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
- build_header(linker, table_data,
- (void *)(table_data->data + table_data->len - dsdt->buf->len),
- "DSDT", dsdt->buf->len, 2, NULL, NULL);
+
+ acpi_table_end(linker, &table);
free_aml_allocator();
}
bool patched;
} AcpiBuildState;
+static void acpi_align_size(GArray *blob, unsigned align)
+{
+ /*
+ * Align size to multiple of given size. This reduces the chance
+ * we need to change size in the future (breaking cross version migration).
+ */
+ g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
+}
+
static
void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
{
dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, vms);
- /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
+ /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
acpi_add_table(table_offsets, tables_blob);
build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, vms);
+ if (!vmc->no_cpu_topology) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_pptt(tables_blob, tables->linker, ms,
+ vms->oem_id, vms->oem_table_id);
+ }
+
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker, vms);
.base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
.size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
};
- build_mcfg(tables_blob, tables->linker, &mcfg);
+ build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
+ vms->oem_table_id);
}
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
+ acpi_add_table(table_offsets, tables_blob);
+ build_dbg2(tables_blob, tables->linker, vms);
+
if (vms->ras) {
build_ghes_error_table(tables->hardware_errors, tables->linker);
acpi_add_table(table_offsets, tables_blob);
- acpi_build_hest(tables_blob, tables->linker);
+ acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
+ vms->oem_table_id);
}
if (ms->numa_state->num_nodes > 0) {
build_srat(tables_blob, tables->linker, vms);
if (ms->numa_state->have_numa_distance) {
acpi_add_table(table_offsets, tables_blob);
- build_slit(tables_blob, tables->linker, ms);
+ build_slit(tables_blob, tables->linker, ms, vms->oem_id,
+ vms->oem_table_id);
}
}
if (ms->nvdimms_state->is_enabled) {
nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
- ms->nvdimms_state, ms->ram_slots);
+ ms->nvdimms_state, ms->ram_slots, vms->oem_id,
+ vms->oem_table_id);
}
if (its_class_name() && !vmc->no_its) {
build_iort(tables_blob, tables->linker, vms);
}
+#ifdef CONFIG_TPM
if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
acpi_add_table(table_offsets, tables_blob);
- build_tpm2(tables_blob, tables->linker, tables->tcpalog);
+ build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
+ vms->oem_table_id);
+ }
+#endif
+
+ if (vms->iommu == VIRT_IOMMU_VIRTIO) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
+ vms->oem_id, vms->oem_table_id);
}
/* XSDT is pointed to by RSDP */
xsdt = tables_blob->len;
- build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
+ build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
+ vms->oem_table_id);
/* RSDP is in FSEG memory, so allocate it separately */
{
AcpiRsdpData rsdp_data = {
.revision = 2,
- .oem_id = ACPI_BUILD_APPNAME6,
+ .oem_id = vms->oem_id,
.xsdt_tbl_offset = &xsdt,
.rsdt_tbl_offset = NULL,
};
build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
}
+ /*
+ * The align size is 128, warn if 64k is not enough therefore
+ * the align size could be resized.
+ */
+ if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
+ warn_report("ACPI table size %u exceeds %d bytes,"
+ " migration may not work",
+ tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
+ error_printf("Try removing CPUs, NUMA nodes, memory slots"
+ " or PCI bridges.");
+ }
+ acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
+
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
/* Now expose it all to Guest */
build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
build_state, tables.table_data,
- ACPI_BUILD_TABLE_FILE,
- ACPI_BUILD_TABLE_MAX_SIZE);
+ ACPI_BUILD_TABLE_FILE);
assert(build_state->table_mr != NULL);
- build_state->linker_mr =
- acpi_add_rom_blob(virt_acpi_build_update, build_state,
- tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
+ build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
+ build_state,
+ tables.linker->cmd_blob,
+ ACPI_BUILD_LOADER_FILE);
fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
acpi_data_len(tables.tcpalog));
build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
build_state, tables.rsdp,
- ACPI_BUILD_RSDP_FILE, 0);
+ ACPI_BUILD_RSDP_FILE);
qemu_register_reset(virt_acpi_build_reset, build_state);
virt_acpi_build_reset(build_state);
projects / qemu.git / blobdiff