usb: add ifnum to USBEndpoint

[qemu.git] / hw / pl031.c

diff --git a/hw/pl031.c b/hw/pl031.c
index 3f8bfaa65b98a4488722c69cd5b12bde580d7644..a007ff0ff249f20eb3bdc2524b14cfd1cc347813 100644 (file)
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -9,18 +9,16 @@
  *
  */
 
-#include "hw.h"
-#include "primecell.h"
+#include "sysbus.h"
 #include "qemu-timer.h"
-#include "sysemu.h"
 
 //#define DEBUG_PL031
 
 #ifdef DEBUG_PL031
-#define DPRINTF(fmt, args...) \
-do { printf("pl031: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) \
+do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...) do {} while(0)
+#define DPRINTF(fmt, ...) do {} while(0)
 #endif
 
 #define RTC_DR      0x00    /* Data read register */
@@ -33,6 +31,8 @@ do { printf("pl031: " fmt , ##args); } while (0)
 #define RTC_ICR     0x1c    /* Interrupt clear register */
 
 typedef struct {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
     QEMUTimer *timer;
     qemu_irq irq;
 
@@ -45,6 +45,21 @@ typedef struct {
     uint32_t is;
 } pl031_state;
 
+static const VMStateDescription vmstate_pl031 = {
+    .name = "pl031",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(tick_offset, pl031_state),
+        VMSTATE_UINT32(mr, pl031_state),
+        VMSTATE_UINT32(lr, pl031_state),
+        VMSTATE_UINT32(cr, pl031_state),
+        VMSTATE_UINT32(im, pl031_state),
+        VMSTATE_UINT32(is, pl031_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const unsigned char pl031_id[] = {
     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
@@ -66,9 +81,9 @@ static void pl031_interrupt(void * opaque)
 
 static uint32_t pl031_get_count(pl031_state *s)
 {
-    /* This assumes qemu_get_clock returns the time since the machine was
+    /* This assumes qemu_get_clock_ns returns the time since the machine was
        created.  */
-    return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
+    return s->tick_offset + qemu_get_clock_ns(vm_clock) / get_ticks_per_sec();
 }
 
 static void pl031_set_alarm(pl031_state *s)
@@ -76,8 +91,8 @@ static void pl031_set_alarm(pl031_state *s)
     int64_t now;
     uint32_t ticks;
 
-    now = qemu_get_clock(vm_clock);
-    ticks = s->tick_offset + now / ticks_per_sec;
+    now = qemu_get_clock_ns(vm_clock);
+    ticks = s->tick_offset + now / get_ticks_per_sec();
 
     /* The timer wraps around.  This subtraction also wraps in the same way,
        and gives correct results when alarm < now_ticks.  */
@@ -87,11 +102,12 @@ static void pl031_set_alarm(pl031_state *s)
         qemu_del_timer(s->timer);
         pl031_interrupt(s);
     } else {
-        qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec);
+        qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
     }
 }
 
-static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
+static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
+                           unsigned size)
 {
     pl031_state *s = (pl031_state *)opaque;
 
@@ -127,7 +143,7 @@ static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
 }
 
 static void pl031_write(void * opaque, target_phys_addr_t offset,
-                        uint32_t value)
+                        uint64_t value, unsigned size)
 {
     pl031_state *s = (pl031_state *)opaque;
 
@@ -147,7 +163,7 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
         pl031_update(s);
         break;
     case RTC_ICR:
-        /* The PL031 documentation (DDI0224B) states that the interupt is
+        /* The PL031 documentation (DDI0224B) states that the interrupt is
            cleared when bit 0 of the written value is set.  However the
            arm926e documentation (DDI0287B) states that the interrupt is
            cleared when any value is written.  */
@@ -172,37 +188,40 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
     }
 }
 
-static CPUWriteMemoryFunc * pl031_writefn[] = {
-    pl031_write,
-    pl031_write,
-    pl031_write
-};
-
-static CPUReadMemoryFunc * pl031_readfn[] = {
-    pl031_read,
-    pl031_read,
-    pl031_read
+static const MemoryRegionOps pl031_ops = {
+    .read = pl031_read,
+    .write = pl031_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-void pl031_init(uint32_t base, qemu_irq irq)
+static int pl031_init(SysBusDevice *dev)
 {
-    int iomemtype;
-    pl031_state *s;
+    pl031_state *s = FROM_SYSBUS(pl031_state, dev);
     struct tm tm;
 
-    s = qemu_mallocz(sizeof(pl031_state));
-
-    iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
-    if (iomemtype == -1) {
-        hw_error("pl031_init: Can't register I/O memory\n");
-    }
-
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
+    sysbus_init_mmio(dev, &s->iomem);
 
-    s->irq  = irq;
+    sysbus_init_irq(dev, &s->irq);
     /* ??? We assume vm_clock is zero at this point.  */
     qemu_get_timedate(&tm, 0);
     s->tick_offset = mktimegm(&tm);
 
-    s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);
+    s->timer = qemu_new_timer_ns(vm_clock, pl031_interrupt, s);
+    return 0;
 }
+
+static SysBusDeviceInfo pl031_info = {
+    .init = pl031_init,
+    .qdev.name = "pl031",
+    .qdev.size = sizeof(pl031_state),
+    .qdev.vmsd = &vmstate_pl031,
+    .qdev.no_user = 1,
+};
+
+static void pl031_register_devices(void)
+{
+    sysbus_register_withprop(&pl031_info);
+}
+
+device_init(pl031_register_devices)