* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "hw.h"
#include "i2c.h"
#include "omap.h"
+#include "sysbus.h"
-struct omap_i2c_s {
- target_phys_addr_t base;
+
+typedef struct OMAPI2CState {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
- i2c_slave slave;
i2c_bus *bus;
uint8_t revision;
+ void *iclk;
+ void *fclk;
+
uint8_t mask;
uint16_t stat;
uint16_t dma;
uint8_t divider;
uint8_t times[2];
uint16_t test;
-};
+} OMAPI2CState;
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
-static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
+static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
qemu_set_irq(s->irq, s->stat & s->mask);
if ((s->dma >> 15) & 1) /* RDMA_EN */
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
}
-/* These are only stubs now. */
-static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event)
-{
- struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-
- if ((~s->control >> 15) & 1) /* I2C_EN */
- return;
-
- switch (event) {
- case I2C_START_SEND:
- case I2C_START_RECV:
- s->stat |= 1 << 9; /* AAS */
- break;
- case I2C_FINISH:
- s->stat |= 1 << 2; /* ARDY */
- break;
- case I2C_NACK:
- s->stat |= 1 << 1; /* NACK */
- break;
- }
-
- omap_i2c_interrupts_update(s);
-}
-
-static int omap_i2c_rx(i2c_slave *i2c)
-{
- struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
- uint8_t ret = 0;
-
- if ((~s->control >> 15) & 1) /* I2C_EN */
- return -1;
-
- if (s->txlen)
- ret = s->fifo >> ((-- s->txlen) << 3) & 0xff;
- else
- s->stat |= 1 << 10; /* XUDF */
- s->stat |= 1 << 4; /* XRDY */
-
- omap_i2c_interrupts_update(s);
- return ret;
-}
-
-static int omap_i2c_tx(i2c_slave *i2c, uint8_t data)
-{
- struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-
- if ((~s->control >> 15) & 1) /* I2C_EN */
- return 1;
-
- if (s->rxlen < 4)
- s->fifo |= data << ((s->rxlen ++) << 3);
- else
- s->stat |= 1 << 11; /* ROVR */
- s->stat |= 1 << 3; /* RRDY */
-
- omap_i2c_interrupts_update(s);
- return 1;
-}
-
-static void omap_i2c_fifo_run(struct omap_i2c_s *s)
+static void omap_i2c_fifo_run(OMAPI2CState *s)
{
int ack = 1;
}
if (ack && s->count_cur)
s->stat |= 1 << 4; /* XRDY */
+ else
+ s->stat &= ~(1 << 4); /* XRDY */
if (!s->count_cur) {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
if (s->rxlen)
s->stat |= 1 << 3; /* RRDY */
+ else
+ s->stat &= ~(1 << 3); /* RRDY */
}
if (!s->count_cur) {
if ((s->control >> 1) & 1) { /* STP */
s->control &= ~(1 << 1); /* STP */
}
-void omap_i2c_reset(struct omap_i2c_s *s)
+static void omap_i2c_reset(DeviceState *dev)
{
+ OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState,
+ sysbus_from_qdev(dev));
s->mask = 0;
s->stat = 0;
s->dma = 0;
static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
{
- struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
+ OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
if (s->rxlen > 2)
s->fifo >>= 16;
s->rxlen -= 2;
- } else
- /* XXX: remote access (qualifier) error - what's that? */;
+ } else {
+ /* XXX: remote access (qualifier) error - what's that? */
+ }
if (!s->rxlen) {
s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */
static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
+ OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
int nack;
return;
}
- s->stat &= ~(value & 0x3f);
+ /* RRDY and XRDY are reset by hardware. (in all versions???) */
+ s->stat &= ~(value & 0x27);
omap_i2c_interrupts_update(s);
break;
}
if (value & 2)
- omap_i2c_reset(s);
+ omap_i2c_reset(&s->busdev.qdev);
break;
case 0x24: /* I2C_CON */
s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV)
- omap_i2c_reset(s);
+ omap_i2c_reset(&s->busdev.qdev);
break;
}
if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
- printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
+ fprintf(stderr, "%s: I^2C slave mode not supported\n",
+ __FUNCTION__);
break;
}
if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
- printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
+ fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
+ __FUNCTION__);
break;
}
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
(~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */
+ s->fifo = 0;
if (nack)
s->control &= ~(1 << 1); /* STP */
else {
case 0x28: /* I2C_OA */
s->addr[0] = value & 0x3ff;
- i2c_set_slave_address(&s->slave, value & 0x7f);
break;
case 0x2c: /* I2C_SA */
omap_i2c_interrupts_update(s);
}
if (value & (1 << 15)) /* ST_EN */
- printf("%s: System Test not supported\n", __FUNCTION__);
+ fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
break;
default:
static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
+ OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
}
}
-static CPUReadMemoryFunc *omap_i2c_readfn[] = {
- omap_badwidth_read16,
- omap_i2c_read,
- omap_badwidth_read16,
+static const MemoryRegionOps omap_i2c_ops = {
+ .old_mmio = {
+ .read = {
+ omap_badwidth_read16,
+ omap_i2c_read,
+ omap_badwidth_read16,
+ },
+ .write = {
+ omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
+ omap_i2c_write,
+ omap_badwidth_write16,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
- omap_i2c_write,
- omap_badwidth_write16,
+static int omap_i2c_init(SysBusDevice *dev)
+{
+ OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, dev);
+
+ if (!s->fclk) {
+ hw_error("omap_i2c: fclk not connected\n");
+ }
+ if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
+ /* Note that OMAP1 doesn't have a separate interface clock */
+ hw_error("omap_i2c: iclk not connected\n");
+ }
+ sysbus_init_irq(dev, &s->irq);
+ sysbus_init_irq(dev, &s->drq[0]);
+ sysbus_init_irq(dev, &s->drq[1]);
+ memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c",
+ (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
+ s->bus = i2c_init_bus(&dev->qdev, NULL);
+ return 0;
+}
+
+static Property omap_i2c_properties[] = {
+ DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
+ DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
+ DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
+ DEFINE_PROP_END_OF_LIST(),
};
-struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
- qemu_irq irq, qemu_irq *dma, omap_clk clk)
+static void omap_i2c_class_init(ObjectClass *klass, void *data)
{
- int iomemtype;
- struct omap_i2c_s *s = (struct omap_i2c_s *)
- qemu_mallocz(sizeof(struct omap_i2c_s));
-
- /* TODO: set a value greater or equal to real hardware */
- s->revision = 0x11;
- s->base = base;
- s->irq = irq;
- s->drq[0] = dma[0];
- s->drq[1] = dma[1];
- s->slave.event = omap_i2c_event;
- s->slave.recv = omap_i2c_rx;
- s->slave.send = omap_i2c_tx;
- s->bus = i2c_init_bus();
- omap_i2c_reset(s);
-
- iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
- omap_i2c_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
-
- return s;
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ k->init = omap_i2c_init;
+ dc->props = omap_i2c_properties;
+ dc->reset = omap_i2c_reset;
}
-struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
- qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
+static TypeInfo omap_i2c_info = {
+ .name = "omap_i2c",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(OMAPI2CState),
+ .class_init = omap_i2c_class_init,
+};
+
+static void omap_i2c_register_types(void)
{
- int iomemtype;
- struct omap_i2c_s *s = (struct omap_i2c_s *)
- qemu_mallocz(sizeof(struct omap_i2c_s));
-
- s->revision = 0x34;
- s->irq = irq;
- s->drq[0] = dma[0];
- s->drq[1] = dma[1];
- s->slave.event = omap_i2c_event;
- s->slave.recv = omap_i2c_rx;
- s->slave.send = omap_i2c_tx;
- s->bus = i2c_init_bus();
- omap_i2c_reset(s);
-
- iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
- omap_i2c_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
-
- return s;
+ type_register_static(&omap_i2c_info);
}
-i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
+i2c_bus *omap_i2c_bus(DeviceState *omap_i2c)
{
+ OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, sysbus_from_qdev(omap_i2c));
return s->bus;
}
+
+type_init(omap_i2c_register_types)
projects / qemu.git / blobdiff