//#define DEBUG_DBDMA
#ifdef DEBUG_DBDMA
-#define DBDMA_DPRINTF(fmt, args...) \
-do { printf("DBDMA: " fmt , ##args); } while (0)
+#define DBDMA_DPRINTF(fmt, ...) \
+ do { printf("DBDMA: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define DBDMA_DPRINTF(fmt, args...)
+#define DBDMA_DPRINTF(fmt, ...)
#endif
/*
int channel;
uint32_t regs[DBDMA_REGS];
qemu_irq irq;
- DBDMA_transfer io;
- DBDMA_transfer_handler transfer_handler;
+ DBDMA_io io;
+ DBDMA_rw rw;
+ DBDMA_flush flush;
dbdma_cmd current;
+ int processing;
} DBDMA_channel;
+typedef struct {
+ MemoryRegion mem;
+ DBDMA_channel channels[DBDMA_CHANNELS];
+} DBDMAState;
+
#ifdef DEBUG_DBDMA
static void dump_dbdma_cmd(dbdma_cmd *cmd)
{
static void dbdma_cmdptr_load(DBDMA_channel *ch)
{
DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
- be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
- cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
+ ch->regs[DBDMA_CMDPTR_LO]);
+ cpu_physical_memory_read(ch->regs[DBDMA_CMDPTR_LO],
(uint8_t*)&ch->current, sizeof(dbdma_cmd));
}
static void dbdma_cmdptr_save(DBDMA_channel *ch)
{
DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
- be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
+ ch->regs[DBDMA_CMDPTR_LO]);
DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
le16_to_cpu(ch->current.xfer_status),
le16_to_cpu(ch->current.res_count));
- cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
+ cpu_physical_memory_write(ch->regs[DBDMA_CMDPTR_LO],
(uint8_t*)&ch->current, sizeof(dbdma_cmd));
}
{
DBDMA_DPRINTF("kill_channel\n");
- ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD);
- ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE);
+ ch->regs[DBDMA_STATUS] |= DEAD;
+ ch->regs[DBDMA_STATUS] &= ~ACTIVE;
qemu_irq_raise(ch->irq);
}
DBDMA_DPRINTF("conditional_interrupt\n");
- intr = be16_to_cpu(current->command) & INTR_MASK;
+ intr = le16_to_cpu(current->command) & INTR_MASK;
switch(intr) {
case INTR_NEVER: /* don't interrupt */
return;
}
- status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
+ status = ch->regs[DBDMA_STATUS] & DEVSTAT;
- sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;
- sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
+ sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f;
+ sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f;
cond = (status & sel_mask) == (sel_value & sel_mask);
DBDMA_DPRINTF("conditional_wait\n");
- wait = be16_to_cpu(current->command) & WAIT_MASK;
+ wait = le16_to_cpu(current->command) & WAIT_MASK;
switch(wait) {
case WAIT_NEVER: /* don't wait */
return 1;
}
- status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
+ status = ch->regs[DBDMA_STATUS] & DEVSTAT;
- sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f;
- sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
+ sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f;
+ sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f;
cond = (status & sel_mask) == (sel_value & sel_mask);
{
uint32_t cp;
- ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT);
+ ch->regs[DBDMA_STATUS] &= ~BT;
- cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]);
- ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
+ cp = ch->regs[DBDMA_CMDPTR_LO];
+ ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd);
dbdma_cmdptr_load(ch);
}
dbdma_cmd *current = &ch->current;
ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
- ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT);
+ ch->regs[DBDMA_STATUS] |= BT;
dbdma_cmdptr_load(ch);
}
/* check if we must branch */
- br = be16_to_cpu(current->command) & BR_MASK;
+ br = le16_to_cpu(current->command) & BR_MASK;
switch(br) {
case BR_NEVER: /* don't branch */
return;
}
- status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
+ status = ch->regs[DBDMA_STATUS] & DEVSTAT;
- sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f;
- sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
+ sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f;
+ sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f;
cond = (status & sel_mask) == (sel_value & sel_mask);
}
}
-static int dbdma_read_memory(DBDMA_transfer *io)
-{
- DBDMA_channel *ch = io->channel;
- dbdma_cmd *current = &ch->current;
-
- DBDMA_DPRINTF("DBDMA_read_memory\n");
-
- cpu_physical_memory_read(le32_to_cpu(current->phy_addr) + io->buf_pos,
- io->buf, io->buf_len);
-
- return io->buf_len;
-}
+static QEMUBH *dbdma_bh;
+static void channel_run(DBDMA_channel *ch);
-static int dbdma_write_memory(DBDMA_transfer *io)
+static void dbdma_end(DBDMA_io *io)
{
DBDMA_channel *ch = io->channel;
dbdma_cmd *current = &ch->current;
- DBDMA_DPRINTF("DBDMA_write_memory\n");
+ if (conditional_wait(ch))
+ goto wait;
+
+ current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
+ current->res_count = cpu_to_le16(io->len);
+ dbdma_cmdptr_save(ch);
+ if (io->is_last)
+ ch->regs[DBDMA_STATUS] &= ~FLUSH;
- cpu_physical_memory_write(le32_to_cpu(current->phy_addr) + io->buf_pos,
- io->buf, io->buf_len);
+ conditional_interrupt(ch);
+ conditional_branch(ch);
- return io->buf_len;
+wait:
+ ch->processing = 0;
+ if ((ch->regs[DBDMA_STATUS] & RUN) &&
+ (ch->regs[DBDMA_STATUS] & ACTIVE))
+ channel_run(ch);
}
-static int start_output(DBDMA_channel *ch, int key, uint32_t addr,
+static void start_output(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t req_count, int is_last)
{
- dbdma_cmd *current = &ch->current;
- uint32_t n;
-
DBDMA_DPRINTF("start_output\n");
/* KEY_REGS, KEY_DEVICE and KEY_STREAM
DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
if (!addr || key > KEY_STREAM3) {
kill_channel(ch);
- return 0;
+ return;
}
- ch->io.buf = NULL;
- ch->io.buf_pos = 0;
- ch->io.buf_len = 0;
+ ch->io.addr = addr;
ch->io.len = req_count;
ch->io.is_last = is_last;
- n = ch->transfer_handler(&ch->io, dbdma_read_memory);
-
- if (conditional_wait(ch))
- return 1;
-
- current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
- current->res_count = cpu_to_le16(0);
- dbdma_cmdptr_save(ch);
-
- conditional_interrupt(ch);
- conditional_branch(ch);
-
- return 1;
+ ch->io.dma_end = dbdma_end;
+ ch->io.is_dma_out = 1;
+ ch->processing = 1;
+ if (ch->rw) {
+ ch->rw(&ch->io);
+ }
}
-static int start_input(DBDMA_channel *ch, int key, uint32_t addr,
+static void start_input(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t req_count, int is_last)
{
- dbdma_cmd *current = &ch->current;
- uint32_t n;
-
DBDMA_DPRINTF("start_input\n");
/* KEY_REGS, KEY_DEVICE and KEY_STREAM
if (!addr || key > KEY_STREAM3) {
kill_channel(ch);
- return 0;
+ return;
}
- ch->io.buf = NULL;
- ch->io.buf_pos = 0;
- ch->io.buf_len = 0;
+ ch->io.addr = addr;
ch->io.len = req_count;
ch->io.is_last = is_last;
- n = ch->transfer_handler(&ch->io, dbdma_write_memory);
-
- if (conditional_wait(ch))
- return 1;
-
- current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
- current->res_count = cpu_to_le16(0);
- dbdma_cmdptr_save(ch);
-
- conditional_interrupt(ch);
- conditional_branch(ch);
-
- return 1;
+ ch->io.dma_end = dbdma_end;
+ ch->io.is_dma_out = 0;
+ ch->processing = 1;
+ if (ch->rw) {
+ ch->rw(&ch->io);
+ }
}
-static int load_word(DBDMA_channel *ch, int key, uint32_t addr,
+static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t len)
{
dbdma_cmd *current = &ch->current;
if (key != KEY_SYSTEM) {
printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
kill_channel(ch);
- return 0;
+ return;
}
cpu_physical_memory_read(addr, (uint8_t*)&val, len);
current->cmd_dep = val;
if (conditional_wait(ch))
- return 1;
+ goto wait;
- current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
+ current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
dbdma_cmdptr_save(ch);
+ ch->regs[DBDMA_STATUS] &= ~FLUSH;
conditional_interrupt(ch);
next(ch);
- return 1;
+wait:
+ qemu_bh_schedule(dbdma_bh);
}
-static int store_word(DBDMA_channel *ch, int key, uint32_t addr,
+static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
uint16_t len)
{
dbdma_cmd *current = &ch->current;
if (key != KEY_SYSTEM) {
printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
kill_channel(ch);
- return 0;
+ return;
}
val = current->cmd_dep;
cpu_physical_memory_write(addr, (uint8_t*)&val, len);
if (conditional_wait(ch))
- return 1;
+ goto wait;
- current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
+ current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
dbdma_cmdptr_save(ch);
+ ch->regs[DBDMA_STATUS] &= ~FLUSH;
conditional_interrupt(ch);
next(ch);
- return 1;
+wait:
+ qemu_bh_schedule(dbdma_bh);
}
-static int nop(DBDMA_channel *ch)
+static void nop(DBDMA_channel *ch)
{
dbdma_cmd *current = &ch->current;
if (conditional_wait(ch))
- return 1;
+ goto wait;
- current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
+ current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
dbdma_cmdptr_save(ch);
conditional_interrupt(ch);
conditional_branch(ch);
- return 1;
+wait:
+ qemu_bh_schedule(dbdma_bh);
}
-static int stop(DBDMA_channel *ch)
+static void stop(DBDMA_channel *ch)
{
- ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD));
+ ch->regs[DBDMA_STATUS] &= ~(ACTIVE|DEAD|FLUSH);
/* the stop command does not increment command pointer */
-
- return 0;
}
-static int channel_run(DBDMA_channel *ch)
+static void channel_run(DBDMA_channel *ch)
{
dbdma_cmd *current = &ch->current;
uint16_t cmd, key;
/* clear WAKE flag at command fetch */
- ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE);
+ ch->regs[DBDMA_STATUS] &= ~WAKE;
cmd = le16_to_cpu(current->command) & COMMAND_MASK;
switch (cmd) {
case DBDMA_NOP:
- return nop(ch);
+ nop(ch);
+ return;
case DBDMA_STOP:
- return stop(ch);
+ stop(ch);
+ return;
}
key = le16_to_cpu(current->command) & 0x0700;
if (key == KEY_STREAM4) {
printf("command %x, invalid key 4\n", cmd);
kill_channel(ch);
- return 0;
+ return;
}
switch (cmd) {
case OUTPUT_MORE:
- return start_output(ch, key, phy_addr, req_count, 0);
+ start_output(ch, key, phy_addr, req_count, 0);
+ return;
case OUTPUT_LAST:
- return start_output(ch, key, phy_addr, req_count, 1);
+ start_output(ch, key, phy_addr, req_count, 1);
+ return;
case INPUT_MORE:
- return start_input(ch, key, phy_addr, req_count, 0);
+ start_input(ch, key, phy_addr, req_count, 0);
+ return;
case INPUT_LAST:
- return start_input(ch, key, phy_addr, req_count, 1);
+ start_input(ch, key, phy_addr, req_count, 1);
+ return;
}
if (key < KEY_REGS) {
switch (cmd) {
case LOAD_WORD:
- return load_word(ch, key, phy_addr, req_count);
+ load_word(ch, key, phy_addr, req_count);
+ return;
case STORE_WORD:
- return store_word(ch, key, phy_addr, req_count);
+ store_word(ch, key, phy_addr, req_count);
+ return;
}
-
- return 0;
}
-static QEMUBH *dbdma_bh;
-
-static void DBDMA_run (DBDMA_channel *ch)
+static void DBDMA_run(DBDMAState *s)
{
int channel;
- int rearm = 0;
-
- for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
- uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
- if ((status & RUN) && (status & ACTIVE)) {
- if (status & FLUSH)
- while (channel_run(ch));
- else if (channel_run(ch))
- rearm = 1;
- }
- ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
- }
- if (rearm)
- qemu_bh_schedule_idle(dbdma_bh);
+ for (channel = 0; channel < DBDMA_CHANNELS; channel++) {
+ DBDMA_channel *ch = &s->channels[channel];
+ uint32_t status = ch->regs[DBDMA_STATUS];
+ if (!ch->processing && (status & RUN) && (status & ACTIVE)) {
+ channel_run(ch);
+ }
+ }
}
static void DBDMA_run_bh(void *opaque)
{
- DBDMA_channel *ch = opaque;
+ DBDMAState *s = opaque;
DBDMA_DPRINTF("DBDMA_run_bh\n");
- DBDMA_run(ch);
+ DBDMA_run(s);
}
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
- DBDMA_transfer_handler transfer_handler,
+ DBDMA_rw rw, DBDMA_flush flush,
void *opaque)
{
- DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
+ DBDMAState *s = dbdma;
+ DBDMA_channel *ch = &s->channels[nchan];
DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
ch->irq = irq;
ch->channel = nchan;
- ch->transfer_handler = transfer_handler;
+ ch->rw = rw;
+ ch->flush = flush;
ch->io.opaque = opaque;
ch->io.channel = ch;
}
-void DBDMA_schedule(void)
-{
- CPUState *env = cpu_single_env;
- if (env)
- cpu_interrupt(env, CPU_INTERRUPT_EXIT);
-}
-
static void
dbdma_control_write(DBDMA_channel *ch)
{
uint16_t mask, value;
uint32_t status;
- mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff;
- value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
+ mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff;
+ value = ch->regs[DBDMA_CONTROL] & 0xffff;
value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
- status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
+ status = ch->regs[DBDMA_STATUS];
status = (value & mask) | (status & ~mask);
}
if (status & PAUSE)
status &= ~ACTIVE;
- if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
+ if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
/* RUN is cleared */
status &= ~(ACTIVE|DEAD);
}
DBDMA_DPRINTF(" status 0x%08x\n", status);
- ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
+ ch->regs[DBDMA_STATUS] = status;
- if (status & ACTIVE) {
- qemu_bh_schedule_idle(dbdma_bh);
- if (status & FLUSH)
- DBDMA_schedule();
- }
+ if (status & ACTIVE)
+ qemu_bh_schedule(dbdma_bh);
+ if ((status & FLUSH) && ch->flush)
+ ch->flush(&ch->io);
}
-static void dbdma_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void dbdma_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
- DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
+ DBDMAState *s = opaque;
+ DBDMA_channel *ch = &s->channels[channel];
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
/* cmdptr cannot be modified if channel is RUN or ACTIVE */
if (reg == DBDMA_CMDPTR_LO &&
- (ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE)))
+ (ch->regs[DBDMA_STATUS] & (RUN | ACTIVE)))
return;
ch->regs[reg] = value;
break;
case DBDMA_CMDPTR_LO:
/* 16-byte aligned */
- ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
+ ch->regs[DBDMA_CMDPTR_LO] &= ~0xf;
dbdma_cmdptr_load(ch);
break;
case DBDMA_STATUS:
}
}
-static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t dbdma_read(void *opaque, hwaddr addr,
+ unsigned size)
{
uint32_t value;
int channel = addr >> DBDMA_CHANNEL_SHIFT;
- DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
+ DBDMAState *s = opaque;
+ DBDMA_channel *ch = &s->channels[channel];
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
value = ch->regs[reg];
return value;
}
-static CPUWriteMemoryFunc *dbdma_write[] = {
- NULL,
- NULL,
- dbdma_writel,
+static const MemoryRegionOps dbdma_ops = {
+ .read = dbdma_read,
+ .write = dbdma_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static CPUReadMemoryFunc *dbdma_read[] = {
- NULL,
- NULL,
- dbdma_readl,
+static const VMStateDescription vmstate_dbdma_channel = {
+ .name = "dbdma_channel",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS),
+ VMSTATE_END_OF_LIST()
+ }
};
-static void dbdma_save(QEMUFile *f, void *opaque)
-{
- DBDMA_channel *s = opaque;
- unsigned int i, j;
-
- for (i = 0; i < DBDMA_CHANNELS; i++)
- for (j = 0; j < DBDMA_REGS; j++)
- qemu_put_be32s(f, &s[i].regs[j]);
-}
-
-static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
-{
- DBDMA_channel *s = opaque;
- unsigned int i, j;
-
- if (version_id != 2)
- return -EINVAL;
-
- for (i = 0; i < DBDMA_CHANNELS; i++)
- for (j = 0; j < DBDMA_REGS; j++)
- qemu_get_be32s(f, &s[i].regs[j]);
-
- return 0;
-}
+static const VMStateDescription vmstate_dbdma = {
+ .name = "dbdma",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1,
+ vmstate_dbdma_channel, DBDMA_channel),
+ VMSTATE_END_OF_LIST()
+ }
+};
static void dbdma_reset(void *opaque)
{
- DBDMA_channel *s = opaque;
+ DBDMAState *s = opaque;
int i;
for (i = 0; i < DBDMA_CHANNELS; i++)
- memset(s[i].regs, 0, DBDMA_SIZE);
+ memset(s->channels[i].regs, 0, DBDMA_SIZE);
}
-void* DBDMA_init (int *dbdma_mem_index)
+void* DBDMA_init (MemoryRegion **dbdma_mem)
{
- DBDMA_channel *s;
+ DBDMAState *s;
- s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
- if (!s)
- return NULL;
+ s = g_malloc0(sizeof(DBDMAState));
- *dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
- register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
+ memory_region_init_io(&s->mem, &dbdma_ops, s, "dbdma", 0x1000);
+ *dbdma_mem = &s->mem;
+ vmstate_register(NULL, -1, &vmstate_dbdma, s);
qemu_register_reset(dbdma_reset, s);
- dbdma_reset(s);
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
projects / qemu.git / blobdiff