#include "exec.h"
#include "host-utils.h"
+#include "helper.h"
//#define DEBUG_PCALL
//#define DEBUG_MMU
//#define DEBUG_MXCC
//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
+//#define DEBUG_ASI
#ifdef DEBUG_MMU
#define DPRINTF_MMU(fmt, args...) \
#define DPRINTF_MXCC(fmt, args...)
#endif
+#ifdef DEBUG_ASI
+#define DPRINTF_ASI(fmt, args...) \
+do { printf("ASI: " fmt , ##args); } while (0)
+#else
+#define DPRINTF_ASI(fmt, args...)
+#endif
+
void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
}
-void check_ieee_exceptions()
+void helper_trap(target_ulong nb_trap)
+{
+ env->exception_index = TT_TRAP + (nb_trap & 0x7f);
+ cpu_loop_exit();
+}
+
+void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
{
- T0 = get_float_exception_flags(&env->fp_status);
- if (T0)
- {
+ if (do_trap) {
+ env->exception_index = TT_TRAP + (nb_trap & 0x7f);
+ cpu_loop_exit();
+ }
+}
+
+void helper_check_ieee_exceptions(void)
+{
+ target_ulong status;
+
+ status = get_float_exception_flags(&env->fp_status);
+ if (status) {
/* Copy IEEE 754 flags into FSR */
- if (T0 & float_flag_invalid)
+ if (status & float_flag_invalid)
env->fsr |= FSR_NVC;
- if (T0 & float_flag_overflow)
+ if (status & float_flag_overflow)
env->fsr |= FSR_OFC;
- if (T0 & float_flag_underflow)
+ if (status & float_flag_underflow)
env->fsr |= FSR_UFC;
- if (T0 & float_flag_divbyzero)
+ if (status & float_flag_divbyzero)
env->fsr |= FSR_DZC;
- if (T0 & float_flag_inexact)
+ if (status & float_flag_inexact)
env->fsr |= FSR_NXC;
- if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
- {
+ if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
/* Unmasked exception, generate a trap */
env->fsr |= FSR_FTT_IEEE_EXCP;
raise_exception(TT_FP_EXCP);
- }
- else
- {
+ } else {
/* Accumulate exceptions */
env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
}
- }
+ }
+}
+
+void helper_clear_float_exceptions(void)
+{
+ set_float_exception_flags(0, &env->fp_status);
}
#ifdef USE_INT_TO_FLOAT_HELPERS
void do_fitos(void)
{
- set_float_exception_flags(0, &env->fp_status);
FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
- check_ieee_exceptions();
}
void do_fitod(void)
{
DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
}
+
+#if defined(CONFIG_USER_ONLY)
+void do_fitoq(void)
+{
+ QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
+}
+#endif
+
#ifdef TARGET_SPARC64
void do_fxtos(void)
{
- set_float_exception_flags(0, &env->fp_status);
FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
- check_ieee_exceptions();
}
void do_fxtod(void)
{
- set_float_exception_flags(0, &env->fp_status);
DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
- check_ieee_exceptions();
+}
+
+#if defined(CONFIG_USER_ONLY)
+void do_fxtoq(void)
+{
+ QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status);
}
#endif
#endif
+#endif
-void do_fabss(void)
+void helper_fabss(void)
{
FT0 = float32_abs(FT1);
}
#ifdef TARGET_SPARC64
-void do_fabsd(void)
+void helper_fabsd(void)
{
DT0 = float64_abs(DT1);
}
+
+#if defined(CONFIG_USER_ONLY)
+void helper_fabsq(void)
+{
+ QT0 = float128_abs(QT1);
+}
+#endif
#endif
-void do_fsqrts(void)
+void helper_fsqrts(void)
{
- set_float_exception_flags(0, &env->fp_status);
FT0 = float32_sqrt(FT1, &env->fp_status);
- check_ieee_exceptions();
}
-void do_fsqrtd(void)
+void helper_fsqrtd(void)
{
- set_float_exception_flags(0, &env->fp_status);
DT0 = float64_sqrt(DT1, &env->fp_status);
- check_ieee_exceptions();
}
+#if defined(CONFIG_USER_ONLY)
+void helper_fsqrtq(void)
+{
+ QT0 = float128_sqrt(QT1, &env->fp_status);
+}
+#endif
+
#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
- void glue(do_, name) (void) \
+ void glue(helper_, name) (void) \
{ \
+ target_ulong new_fsr; \
+ \
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
case float_relation_unordered: \
- T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
+ new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
if ((env->fsr & FSR_NVM) || TRAP) { \
- env->fsr |= T0; \
+ env->fsr |= new_fsr; \
env->fsr |= FSR_NVC; \
env->fsr |= FSR_FTT_IEEE_EXCP; \
raise_exception(TT_FP_EXCP); \
} \
break; \
case float_relation_less: \
- T0 = FSR_FCC0 << FS; \
+ new_fsr = FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
- T0 = FSR_FCC1 << FS; \
+ new_fsr = FSR_FCC1 << FS; \
break; \
default: \
- T0 = 0; \
+ new_fsr = 0; \
break; \
} \
- env->fsr |= T0; \
+ env->fsr |= new_fsr; \
}
GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
+#ifdef CONFIG_USER_ONLY
+GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
+GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
+#endif
+
#ifdef TARGET_SPARC64
GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
+#ifdef CONFIG_USER_ONLY
+GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
+GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
+GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
+GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
+GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
+GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
+#endif
#endif
-#ifndef TARGET_SPARC64
-#ifndef CONFIG_USER_ONLY
-
-#ifdef DEBUG_MXCC
+#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
static void dump_mxcc(CPUState *env)
{
printf("mxccdata: %016llx %016llx %016llx %016llx\n",
}
#endif
-void helper_ld_asi(int asi, int size, int sign)
+#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
+ && defined(DEBUG_ASI)
+static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
+ uint64_t r1)
{
- uint32_t ret = 0;
- uint64_t tmp;
-#ifdef DEBUG_MXCC
- uint32_t last_T0 = T0;
+ switch (size)
+ {
+ case 1:
+ DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
+ addr, asi, r1 & 0xff);
+ break;
+ case 2:
+ DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
+ addr, asi, r1 & 0xffff);
+ break;
+ case 4:
+ DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
+ addr, asi, r1 & 0xffffffff);
+ break;
+ case 8:
+ DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
+ addr, asi, r1);
+ break;
+ }
+}
+#endif
+
+#ifndef TARGET_SPARC64
+#ifndef CONFIG_USER_ONLY
+uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
+{
+ uint64_t ret = 0;
+#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
+ uint32_t last_addr = addr;
#endif
switch (asi) {
case 2: /* SuperSparc MXCC registers */
- switch (T0) {
+ switch (addr) {
case 0x01c00a00: /* MXCC control register */
- if (size == 8) {
+ if (size == 8)
ret = env->mxccregs[3];
- T0 = env->mxccregs[3] >> 32;
- } else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ else
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00a04: /* MXCC control register */
if (size == 4)
ret = env->mxccregs[3];
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
- case 0x01c00f00: /* MBus port address register */
+ case 0x01c00c00: /* Module reset register */
if (size == 8) {
- ret = env->mxccregs[7];
- T0 = env->mxccregs[7] >> 32;
+ ret = env->mxccregs[5];
+ // should we do something here?
} else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
+ break;
+ case 0x01c00f00: /* MBus port address register */
+ if (size == 8)
+ ret = env->mxccregs[7];
+ else
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
default:
- DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
break;
}
- DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
- "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
+ DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
+ "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
#ifdef DEBUG_MXCC
dump_mxcc(env);
#endif
{
int mmulev;
- mmulev = (T0 >> 8) & 15;
+ mmulev = (addr >> 8) & 15;
if (mmulev > 4)
ret = 0;
- else {
- ret = mmu_probe(env, T0, mmulev);
- //bswap32s(&ret);
- }
- DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
+ else
+ ret = mmu_probe(env, addr, mmulev);
+ DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
+ addr, mmulev, ret);
}
break;
case 4: /* read MMU regs */
{
- int reg = (T0 >> 8) & 0xf;
+ int reg = (addr >> 8) & 0x1f;
ret = env->mmuregs[reg];
if (reg == 3) /* Fault status cleared on read */
- env->mmuregs[reg] = 0;
- DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
+ env->mmuregs[3] = 0;
+ else if (reg == 0x13) /* Fault status read */
+ ret = env->mmuregs[3];
+ else if (reg == 0x14) /* Fault address read */
+ ret = env->mmuregs[4];
+ DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
}
break;
+ case 5: // Turbosparc ITLB Diagnostic
+ case 6: // Turbosparc DTLB Diagnostic
+ case 7: // Turbosparc IOTLB Diagnostic
+ break;
case 9: /* Supervisor code access */
switch(size) {
case 1:
- ret = ldub_code(T0);
+ ret = ldub_code(addr);
break;
case 2:
- ret = lduw_code(T0 & ~1);
+ ret = lduw_code(addr & ~1);
break;
default:
case 4:
- ret = ldl_code(T0 & ~3);
+ ret = ldl_code(addr & ~3);
break;
case 8:
- tmp = ldq_code(T0 & ~7);
- ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ ret = ldq_code(addr & ~7);
break;
}
break;
case 0xa: /* User data access */
switch(size) {
case 1:
- ret = ldub_user(T0);
+ ret = ldub_user(addr);
break;
case 2:
- ret = lduw_user(T0 & ~1);
+ ret = lduw_user(addr & ~1);
break;
default:
case 4:
- ret = ldl_user(T0 & ~3);
+ ret = ldl_user(addr & ~3);
break;
case 8:
- tmp = ldq_user(T0 & ~7);
- ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ ret = ldq_user(addr & ~7);
break;
}
break;
case 0xb: /* Supervisor data access */
switch(size) {
case 1:
- ret = ldub_kernel(T0);
+ ret = ldub_kernel(addr);
break;
case 2:
- ret = lduw_kernel(T0 & ~1);
+ ret = lduw_kernel(addr & ~1);
break;
default:
case 4:
- ret = ldl_kernel(T0 & ~3);
+ ret = ldl_kernel(addr & ~3);
break;
case 8:
- tmp = ldq_kernel(T0 & ~7);
- ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ ret = ldq_kernel(addr & ~7);
break;
}
break;
case 0x20: /* MMU passthrough */
switch(size) {
case 1:
- ret = ldub_phys(T0);
+ ret = ldub_phys(addr);
break;
case 2:
- ret = lduw_phys(T0 & ~1);
+ ret = lduw_phys(addr & ~1);
break;
default:
case 4:
- ret = ldl_phys(T0 & ~3);
+ ret = ldl_phys(addr & ~3);
break;
case 8:
- tmp = ldq_phys(T0 & ~7);
- ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
+ ret = ldq_phys(addr & ~7);
break;
}
break;
- case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
- case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
+ case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
switch(size) {
case 1:
- ret = ldub_phys((target_phys_addr_t)T0
+ ret = ldub_phys((target_phys_addr_t)addr
| ((target_phys_addr_t)(asi & 0xf) << 32));
break;
case 2:
- ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
+ ret = lduw_phys((target_phys_addr_t)(addr & ~1)
| ((target_phys_addr_t)(asi & 0xf) << 32));
break;
default:
case 4:
- ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
+ ret = ldl_phys((target_phys_addr_t)(addr & ~3)
| ((target_phys_addr_t)(asi & 0xf) << 32));
break;
case 8:
- tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
+ ret = ldq_phys((target_phys_addr_t)(addr & ~7)
| ((target_phys_addr_t)(asi & 0xf) << 32));
- ret = tmp >> 32;
- T0 = tmp & 0xffffffff;
break;
}
break;
- case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
+ case 0x30: // Turbosparc secondary cache diagnostic
+ case 0x31: // Turbosparc RAM snoop
+ case 0x32: // Turbosparc page table descriptor diagnostic
+ case 0x39: /* data cache diagnostic register */
+ ret = 0;
+ break;
+ case 8: /* User code access, XXX */
default:
- do_unassigned_access(T0, 0, 0, 1);
+ do_unassigned_access(addr, 0, 0, asi);
ret = 0;
break;
}
if (sign) {
switch(size) {
case 1:
- T1 = (int8_t) ret;
+ ret = (int8_t) ret;
break;
case 2:
- T1 = (int16_t) ret;
+ ret = (int16_t) ret;
+ break;
+ case 4:
+ ret = (int32_t) ret;
break;
default:
- T1 = ret;
break;
}
}
- else
- T1 = ret;
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return ret;
}
-void helper_st_asi(int asi, int size)
+void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
{
switch(asi) {
case 2: /* SuperSparc MXCC registers */
- switch (T0) {
+ switch (addr) {
case 0x01c00000: /* MXCC stream data register 0 */
if (size == 8)
- env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;
+ env->mxccdata[0] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00008: /* MXCC stream data register 1 */
if (size == 8)
- env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;
+ env->mxccdata[1] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00010: /* MXCC stream data register 2 */
if (size == 8)
- env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;
+ env->mxccdata[2] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00018: /* MXCC stream data register 3 */
if (size == 8)
- env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;
+ env->mxccdata[3] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00100: /* MXCC stream source */
if (size == 8)
- env->mxccregs[0] = ((uint64_t)T1 << 32) | T2;
+ env->mxccregs[0] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
break;
case 0x01c00200: /* MXCC stream destination */
if (size == 8)
- env->mxccregs[1] = ((uint64_t)T1 << 32) | T2;
+ env->mxccregs[1] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
break;
case 0x01c00a00: /* MXCC control register */
if (size == 8)
- env->mxccregs[3] = ((uint64_t)T1 << 32) | T2;
+ env->mxccregs[3] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00a04: /* MXCC control register */
if (size == 4)
- env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1;
+ env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00e00: /* MXCC error register */
+ // writing a 1 bit clears the error
if (size == 8)
- env->mxccregs[6] = ((uint64_t)T1 << 32) | T2;
+ env->mxccregs[6] &= ~val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
- if (env->mxccregs[6] == 0xffffffffffffffffULL) {
- // this is probably a reset
- }
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
case 0x01c00f00: /* MBus port address register */
if (size == 8)
- env->mxccregs[7] = ((uint64_t)T1 << 32) | T2;
+ env->mxccregs[7] = val;
else
- DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
break;
default:
- DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
+ DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
break;
}
- DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
+ DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
#ifdef DEBUG_MXCC
dump_mxcc(env);
#endif
{
int mmulev;
- mmulev = (T0 >> 8) & 15;
+ mmulev = (addr >> 8) & 15;
DPRINTF_MMU("mmu flush level %d\n", mmulev);
switch (mmulev) {
case 0: // flush page
- tlb_flush_page(env, T0 & 0xfffff000);
+ tlb_flush_page(env, addr & 0xfffff000);
break;
case 1: // flush segment (256k)
case 2: // flush region (16M)
#ifdef DEBUG_MMU
dump_mmu(env);
#endif
- return;
}
+ break;
case 4: /* write MMU regs */
{
- int reg = (T0 >> 8) & 0xf;
+ int reg = (addr >> 8) & 0x1f;
uint32_t oldreg;
oldreg = env->mmuregs[reg];
switch(reg) {
- case 0:
- env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM);
- env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM);
+ case 0: // Control Register
+ env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
+ (val & 0x00ffffff);
// Mappings generated during no-fault mode or MMU
// disabled mode are invalid in normal mode
- if (oldreg != env->mmuregs[reg])
+ if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
+ (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
tlb_flush(env, 1);
break;
- case 2:
- env->mmuregs[reg] = T1;
+ case 1: // Context Table Pointer Register
+ env->mmuregs[reg] = val & env->mmu_ctpr_mask;
+ break;
+ case 2: // Context Register
+ env->mmuregs[reg] = val & env->mmu_cxr_mask;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
tlb_flush(env, 1);
}
break;
- case 3:
- case 4:
+ case 3: // Synchronous Fault Status Register with Clear
+ case 4: // Synchronous Fault Address Register
+ break;
+ case 0x10: // TLB Replacement Control Register
+ env->mmuregs[reg] = val & env->mmu_trcr_mask;
+ break;
+ case 0x13: // Synchronous Fault Status Register with Read and Clear
+ env->mmuregs[3] = val & env->mmu_sfsr_mask;
+ break;
+ case 0x14: // Synchronous Fault Address Register
+ env->mmuregs[4] = val;
break;
default:
- env->mmuregs[reg] = T1;
+ env->mmuregs[reg] = val;
break;
}
if (oldreg != env->mmuregs[reg]) {
#ifdef DEBUG_MMU
dump_mmu(env);
#endif
- return;
}
+ break;
+ case 5: // Turbosparc ITLB Diagnostic
+ case 6: // Turbosparc DTLB Diagnostic
+ case 7: // Turbosparc IOTLB Diagnostic
+ break;
case 0xa: /* User data access */
switch(size) {
case 1:
- stb_user(T0, T1);
+ stb_user(addr, val);
break;
case 2:
- stw_user(T0 & ~1, T1);
+ stw_user(addr & ~1, val);
break;
default:
case 4:
- stl_user(T0 & ~3, T1);
+ stl_user(addr & ~3, val);
break;
case 8:
- stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
+ stq_user(addr & ~7, val);
break;
}
break;
case 0xb: /* Supervisor data access */
switch(size) {
case 1:
- stb_kernel(T0, T1);
+ stb_kernel(addr, val);
break;
case 2:
- stw_kernel(T0 & ~1, T1);
+ stw_kernel(addr & ~1, val);
break;
default:
case 4:
- stl_kernel(T0 & ~3, T1);
+ stl_kernel(addr & ~3, val);
break;
case 8:
- stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
+ stq_kernel(addr & ~7, val);
break;
}
break;
break;
case 0x17: /* Block copy, sta access */
{
- // value (T1) = src
- // address (T0) = dst
+ // val = src
+ // addr = dst
// copy 32 bytes
unsigned int i;
- uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
+ uint32_t src = val & ~3, dst = addr & ~3, temp;
for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
temp = ldl_kernel(src);
stl_kernel(dst, temp);
}
}
- return;
+ break;
case 0x1f: /* Block fill, stda access */
{
- // value (T1, T2)
- // address (T0) = dst
- // fill 32 bytes
+ // addr = dst
+ // fill 32 bytes with val
unsigned int i;
- uint32_t dst = T0 & 7;
- uint64_t val;
-
- val = (((uint64_t)T1) << 32) | T2;
+ uint32_t dst = addr & 7;
for (i = 0; i < 32; i += 8, dst += 8)
stq_kernel(dst, val);
}
- return;
+ break;
case 0x20: /* MMU passthrough */
{
switch(size) {
case 1:
- stb_phys(T0, T1);
+ stb_phys(addr, val);
break;
case 2:
- stw_phys(T0 & ~1, T1);
+ stw_phys(addr & ~1, val);
break;
case 4:
default:
- stl_phys(T0 & ~3, T1);
+ stl_phys(addr & ~3, val);
break;
case 8:
- stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
+ stq_phys(addr & ~7, val);
break;
}
}
- return;
- case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
- case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
+ break;
+ case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
{
switch(size) {
case 1:
- stb_phys((target_phys_addr_t)T0
- | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ stb_phys((target_phys_addr_t)addr
+ | ((target_phys_addr_t)(asi & 0xf) << 32), val);
break;
case 2:
- stw_phys((target_phys_addr_t)(T0 & ~1)
- | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ stw_phys((target_phys_addr_t)(addr & ~1)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), val);
break;
case 4:
default:
- stl_phys((target_phys_addr_t)(T0 & ~3)
- | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ stl_phys((target_phys_addr_t)(addr & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), val);
break;
case 8:
- stq_phys((target_phys_addr_t)(T0 & ~7)
- | ((target_phys_addr_t)(asi & 0xf) << 32),
- ((uint64_t)T1 << 32) | T2);
+ stq_phys((target_phys_addr_t)(addr & ~7)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), val);
break;
}
}
- return;
- case 0x31: /* Ross RT620 I-cache flush */
+ break;
+ case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
+ case 0x31: // store buffer data, Ross RT620 I-cache flush or
+ // Turbosparc snoop RAM
+ case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
+ case 0x38: /* breakpoint diagnostics */
+ case 0x4c: /* breakpoint action */
break;
+ case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
- case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
default:
- do_unassigned_access(T0, 1, 0, 1);
- return;
+ do_unassigned_access(addr, 1, 0, asi);
+ break;
}
+#ifdef DEBUG_ASI
+ dump_asi("write", addr, asi, size, val);
+#endif
}
#endif /* CONFIG_USER_ONLY */
#else /* TARGET_SPARC64 */
#ifdef CONFIG_USER_ONLY
-void helper_ld_asi(int asi, int size, int sign)
+uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
{
uint64_t ret = 0;
+#if defined(DEBUG_ASI)
+ target_ulong last_addr = addr;
+#endif
if (asi < 0x80)
raise_exception(TT_PRIV_ACT);
{
switch(size) {
case 1:
- ret = ldub_raw(T0);
+ ret = ldub_raw(addr);
break;
case 2:
- ret = lduw_raw(T0 & ~1);
+ ret = lduw_raw(addr & ~1);
break;
case 4:
- ret = ldl_raw(T0 & ~3);
+ ret = ldl_raw(addr & ~3);
break;
default:
case 8:
- ret = ldq_raw(T0 & ~7);
+ ret = ldq_raw(addr & ~7);
break;
}
}
break;
}
}
- T1 = ret;
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return ret;
}
-void helper_st_asi(int asi, int size)
+void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
{
+#ifdef DEBUG_ASI
+ dump_asi("write", addr, asi, size, val);
+#endif
if (asi < 0x80)
raise_exception(TT_PRIV_ACT);
case 0x89: // Secondary LE
switch(size) {
case 2:
- T0 = bswap16(T0);
+ addr = bswap16(addr);
break;
case 4:
- T0 = bswap32(T0);
+ addr = bswap32(addr);
break;
case 8:
- T0 = bswap64(T0);
+ addr = bswap64(addr);
break;
default:
break;
{
switch(size) {
case 1:
- stb_raw(T0, T1);
+ stb_raw(addr, val);
break;
case 2:
- stw_raw(T0 & ~1, T1);
+ stw_raw(addr & ~1, val);
break;
case 4:
- stl_raw(T0 & ~3, T1);
+ stl_raw(addr & ~3, val);
break;
case 8:
default:
- stq_raw(T0 & ~7, T1);
+ stq_raw(addr & ~7, val);
break;
}
}
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
- do_unassigned_access(T0, 1, 0, 1);
+ do_unassigned_access(addr, 1, 0, 1);
return;
}
}
#else /* CONFIG_USER_ONLY */
-void helper_ld_asi(int asi, int size, int sign)
+uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
{
uint64_t ret = 0;
+#if defined(DEBUG_ASI)
+ target_ulong last_addr = addr;
+#endif
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
if (env->hpstate & HS_PRIV) {
switch(size) {
case 1:
- ret = ldub_hypv(T0);
+ ret = ldub_hypv(addr);
break;
case 2:
- ret = lduw_hypv(T0 & ~1);
+ ret = lduw_hypv(addr & ~1);
break;
case 4:
- ret = ldl_hypv(T0 & ~3);
+ ret = ldl_hypv(addr & ~3);
break;
default:
case 8:
- ret = ldq_hypv(T0 & ~7);
+ ret = ldq_hypv(addr & ~7);
break;
}
} else {
switch(size) {
case 1:
- ret = ldub_kernel(T0);
+ ret = ldub_kernel(addr);
break;
case 2:
- ret = lduw_kernel(T0 & ~1);
+ ret = lduw_kernel(addr & ~1);
break;
case 4:
- ret = ldl_kernel(T0 & ~3);
+ ret = ldl_kernel(addr & ~3);
break;
default:
case 8:
- ret = ldq_kernel(T0 & ~7);
+ ret = ldq_kernel(addr & ~7);
break;
}
}
} else {
switch(size) {
case 1:
- ret = ldub_user(T0);
+ ret = ldub_user(addr);
break;
case 2:
- ret = lduw_user(T0 & ~1);
+ ret = lduw_user(addr & ~1);
break;
case 4:
- ret = ldl_user(T0 & ~3);
+ ret = ldl_user(addr & ~3);
break;
default:
case 8:
- ret = ldq_user(T0 & ~7);
+ ret = ldq_user(addr & ~7);
break;
}
}
{
switch(size) {
case 1:
- ret = ldub_phys(T0);
+ ret = ldub_phys(addr);
break;
case 2:
- ret = lduw_phys(T0 & ~1);
+ ret = lduw_phys(addr & ~1);
break;
case 4:
- ret = ldl_phys(T0 & ~3);
+ ret = ldl_phys(addr & ~3);
break;
default:
case 8:
- ret = ldq_phys(T0 & ~7);
+ ret = ldq_phys(addr & ~7);
break;
}
break;
break;
case 0x50: // I-MMU regs
{
- int reg = (T0 >> 3) & 0xf;
+ int reg = (addr >> 3) & 0xf;
ret = env->immuregs[reg];
break;
for (i = 0; i < 64; i++) {
// Valid, ctx match, vaddr match
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
- env->itlb_tag[i] == T0) {
+ env->itlb_tag[i] == addr) {
ret = env->itlb_tag[i];
break;
}
}
case 0x58: // D-MMU regs
{
- int reg = (T0 >> 3) & 0xf;
+ int reg = (addr >> 3) & 0xf;
ret = env->dmmuregs[reg];
break;
for (i = 0; i < 64; i++) {
// Valid, ctx match, vaddr match
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
- env->dtlb_tag[i] == T0) {
+ env->dtlb_tag[i] == addr) {
ret = env->dtlb_tag[i];
break;
}
case 0x5f: // D-MMU demap, WO
case 0x77: // Interrupt vector, WO
default:
- do_unassigned_access(T0, 0, 0, 1);
+ do_unassigned_access(addr, 0, 0, 1);
ret = 0;
break;
}
break;
}
}
- T1 = ret;
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return ret;
}
-void helper_st_asi(int asi, int size)
+void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
{
+#ifdef DEBUG_ASI
+ dump_asi("write", addr, asi, size, val);
+#endif
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
raise_exception(TT_PRIV_ACT);
case 0x89: // Secondary LE
switch(size) {
case 2:
- T0 = bswap16(T0);
+ addr = bswap16(addr);
break;
case 4:
- T0 = bswap32(T0);
+ addr = bswap32(addr);
break;
case 8:
- T0 = bswap64(T0);
+ addr = bswap64(addr);
break;
default:
break;
if (env->hpstate & HS_PRIV) {
switch(size) {
case 1:
- stb_hypv(T0, T1);
+ stb_hypv(addr, val);
break;
case 2:
- stw_hypv(T0 & ~1, T1);
+ stw_hypv(addr & ~1, val);
break;
case 4:
- stl_hypv(T0 & ~3, T1);
+ stl_hypv(addr & ~3, val);
break;
case 8:
default:
- stq_hypv(T0 & ~7, T1);
+ stq_hypv(addr & ~7, val);
break;
}
} else {
switch(size) {
case 1:
- stb_kernel(T0, T1);
+ stb_kernel(addr, val);
break;
case 2:
- stw_kernel(T0 & ~1, T1);
+ stw_kernel(addr & ~1, val);
break;
case 4:
- stl_kernel(T0 & ~3, T1);
+ stl_kernel(addr & ~3, val);
break;
case 8:
default:
- stq_kernel(T0 & ~7, T1);
+ stq_kernel(addr & ~7, val);
break;
}
}
} else {
switch(size) {
case 1:
- stb_user(T0, T1);
+ stb_user(addr, val);
break;
case 2:
- stw_user(T0 & ~1, T1);
+ stw_user(addr & ~1, val);
break;
case 4:
- stl_user(T0 & ~3, T1);
+ stl_user(addr & ~3, val);
break;
case 8:
default:
- stq_user(T0 & ~7, T1);
+ stq_user(addr & ~7, val);
break;
}
}
{
switch(size) {
case 1:
- stb_phys(T0, T1);
+ stb_phys(addr, val);
break;
case 2:
- stw_phys(T0 & ~1, T1);
+ stw_phys(addr & ~1, val);
break;
case 4:
- stl_phys(T0 & ~3, T1);
+ stl_phys(addr & ~3, val);
break;
case 8:
default:
- stq_phys(T0 & ~7, T1);
+ stq_phys(addr & ~7, val);
break;
}
}
uint64_t oldreg;
oldreg = env->lsu;
- env->lsu = T1 & (DMMU_E | IMMU_E);
+ env->lsu = val & (DMMU_E | IMMU_E);
// Mappings generated during D/I MMU disabled mode are
// invalid in normal mode
if (oldreg != env->lsu) {
}
case 0x50: // I-MMU regs
{
- int reg = (T0 >> 3) & 0xf;
+ int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
oldreg = env->immuregs[reg];
case 8:
return;
case 3: // SFSR
- if ((T1 & 1) == 0)
- T1 = 0; // Clear SFSR
+ if ((val & 1) == 0)
+ val = 0; // Clear SFSR
break;
case 5: // TSB access
case 6: // Tag access
default:
break;
}
- env->immuregs[reg] = T1;
+ env->immuregs[reg] = val;
if (oldreg != env->immuregs[reg]) {
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
}
for (i = 0; i < 64; i++) {
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
env->itlb_tag[i] = env->immuregs[6];
- env->itlb_tte[i] = T1;
+ env->itlb_tte[i] = val;
return;
}
}
for (i = 0; i < 64; i++) {
if ((env->itlb_tte[i] & 0x40) == 0) {
env->itlb_tag[i] = env->immuregs[6];
- env->itlb_tte[i] = T1;
+ env->itlb_tte[i] = val;
return;
}
}
}
case 0x55: // I-MMU data access
{
- unsigned int i = (T0 >> 3) & 0x3f;
+ unsigned int i = (addr >> 3) & 0x3f;
env->itlb_tag[i] = env->immuregs[6];
- env->itlb_tte[i] = T1;
+ env->itlb_tte[i] = val;
return;
}
case 0x57: // I-MMU demap
return;
case 0x58: // D-MMU regs
{
- int reg = (T0 >> 3) & 0xf;
+ int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
oldreg = env->dmmuregs[reg];
case 4:
return;
case 3: // SFSR
- if ((T1 & 1) == 0) {
- T1 = 0; // Clear SFSR, Fault address
+ if ((val & 1) == 0) {
+ val = 0; // Clear SFSR, Fault address
env->dmmuregs[4] = 0;
}
- env->dmmuregs[reg] = T1;
+ env->dmmuregs[reg] = val;
break;
case 1: // Primary context
case 2: // Secondary context
default:
break;
}
- env->dmmuregs[reg] = T1;
+ env->dmmuregs[reg] = val;
if (oldreg != env->dmmuregs[reg]) {
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
}
for (i = 0; i < 64; i++) {
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
env->dtlb_tag[i] = env->dmmuregs[6];
- env->dtlb_tte[i] = T1;
+ env->dtlb_tte[i] = val;
return;
}
}
for (i = 0; i < 64; i++) {
if ((env->dtlb_tte[i] & 0x40) == 0) {
env->dtlb_tag[i] = env->dmmuregs[6];
- env->dtlb_tte[i] = T1;
+ env->dtlb_tte[i] = val;
return;
}
}
}
case 0x5d: // D-MMU data access
{
- unsigned int i = (T0 >> 3) & 0x3f;
+ unsigned int i = (addr >> 3) & 0x3f;
env->dtlb_tag[i] = env->dmmuregs[6];
- env->dtlb_tte[i] = T1;
+ env->dtlb_tte[i] = val;
return;
}
case 0x5f: // D-MMU demap
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
- do_unassigned_access(T0, 1, 0, 1);
+ do_unassigned_access(addr, 1, 0, 1);
return;
}
}
#endif /* CONFIG_USER_ONLY */
-void helper_ldf_asi(int asi, int size, int rd)
+void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
{
- target_ulong tmp_T0 = T0, tmp_T1 = T1;
unsigned int i;
+ target_ulong val;
switch (asi) {
case 0xf0: // Block load primary
raise_exception(TT_ILL_INSN);
return;
}
- if (T0 & 0x3f) {
+ if (addr & 0x3f) {
raise_exception(TT_UNALIGNED);
return;
}
for (i = 0; i < 16; i++) {
- helper_ld_asi(asi & 0x8f, 4, 0);
- *(uint32_t *)&env->fpr[rd++] = T1;
- T0 += 4;
+ *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
+ addr += 4;
}
- T0 = tmp_T0;
- T1 = tmp_T1;
return;
default:
break;
}
- helper_ld_asi(asi, size, 0);
+ val = helper_ld_asi(addr, asi, size, 0);
switch(size) {
default:
case 4:
- *((uint32_t *)&FT0) = T1;
+ *((uint32_t *)&FT0) = val;
break;
case 8:
- *((int64_t *)&DT0) = T1;
+ *((int64_t *)&DT0) = val;
+ break;
+#if defined(CONFIG_USER_ONLY)
+ case 16:
+ // XXX
break;
+#endif
}
- T1 = tmp_T1;
}
-void helper_stf_asi(int asi, int size, int rd)
+void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
{
- target_ulong tmp_T0 = T0, tmp_T1 = T1;
unsigned int i;
+ target_ulong val = 0;
switch (asi) {
case 0xf0: // Block store primary
raise_exception(TT_ILL_INSN);
return;
}
- if (T0 & 0x3f) {
+ if (addr & 0x3f) {
raise_exception(TT_UNALIGNED);
return;
}
for (i = 0; i < 16; i++) {
- T1 = *(uint32_t *)&env->fpr[rd++];
- helper_st_asi(asi & 0x8f, 4);
- T0 += 4;
+ val = *(uint32_t *)&env->fpr[rd++];
+ helper_st_asi(addr, val, asi & 0x8f, 4);
+ addr += 4;
}
- T0 = tmp_T0;
- T1 = tmp_T1;
return;
default:
switch(size) {
default:
case 4:
- T1 = *((uint32_t *)&FT0);
+ val = *((uint32_t *)&FT0);
break;
case 8:
- T1 = *((int64_t *)&DT0);
+ val = *((int64_t *)&DT0);
+ break;
+#if defined(CONFIG_USER_ONLY)
+ case 16:
+ // XXX
break;
+#endif
}
- helper_st_asi(asi, size);
- T1 = tmp_T1;
+ helper_st_asi(addr, val, asi, size);
+}
+
+target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
+ target_ulong val2, uint32_t asi)
+{
+ target_ulong ret;
+
+ val1 &= 0xffffffffUL;
+ ret = helper_ld_asi(addr, asi, 4, 0);
+ ret &= 0xffffffffUL;
+ if (val1 == ret)
+ helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
+ return ret;
}
+target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
+ target_ulong val2, uint32_t asi)
+{
+ target_ulong ret;
+
+ ret = helper_ld_asi(addr, asi, 8, 0);
+ if (val1 == ret)
+ helper_st_asi(addr, val2, asi, 8);
+ return ret;
+}
#endif /* TARGET_SPARC64 */
#ifndef TARGET_SPARC64
-void helper_rett()
+void helper_rett(void)
{
unsigned int cwp;
}
#endif
+target_ulong helper_udiv(target_ulong a, target_ulong b)
+{
+ uint64_t x0;
+ uint32_t x1;
+
+ x0 = a | ((uint64_t) (env->y) << 32);
+ x1 = b;
+
+ if (x1 == 0) {
+ raise_exception(TT_DIV_ZERO);
+ }
+
+ x0 = x0 / x1;
+ if (x0 > 0xffffffff) {
+ env->cc_src2 = 1;
+ return 0xffffffff;
+ } else {
+ env->cc_src2 = 0;
+ return x0;
+ }
+}
+
+target_ulong helper_sdiv(target_ulong a, target_ulong b)
+{
+ int64_t x0;
+ int32_t x1;
+
+ x0 = a | ((int64_t) (env->y) << 32);
+ x1 = b;
+
+ if (x1 == 0) {
+ raise_exception(TT_DIV_ZERO);
+ }
+
+ x0 = x0 / x1;
+ if ((int32_t) x0 != x0) {
+ env->cc_src2 = 1;
+ return x0 < 0? 0x80000000: 0x7fffffff;
+ } else {
+ env->cc_src2 = 0;
+ return x0;
+ }
+}
+
+uint64_t helper_pack64(target_ulong high, target_ulong low)
+{
+ return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
+}
+
void helper_ldfsr(void)
{
int rnd_mode;
+
+ PUT_FSR32(env, *((uint32_t *) &FT0));
switch (env->fsr & FSR_RD_MASK) {
case FSR_RD_NEAREST:
rnd_mode = float_round_nearest_even;
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
-void helper_debug()
+void helper_stfsr(void)
+{
+ *((uint32_t *) &FT0) = GET_FSR32(env);
+}
+
+void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
}
#ifndef TARGET_SPARC64
-void do_wrpsr()
+void helper_wrpsr(target_ulong new_psr)
{
- if ((T0 & PSR_CWP) >= NWINDOWS)
+ if ((new_psr & PSR_CWP) >= NWINDOWS)
raise_exception(TT_ILL_INSN);
else
- PUT_PSR(env, T0);
+ PUT_PSR(env, new_psr);
}
-void do_rdpsr()
+target_ulong helper_rdpsr(void)
{
- T0 = GET_PSR(env);
+ return GET_PSR(env);
}
#else
+target_ulong helper_rdccr(void)
+{
+ return GET_CCR(env);
+}
+
+void helper_wrccr(target_ulong new_ccr)
+{
+ PUT_CCR(env, new_ccr);
+}
+
+// CWP handling is reversed in V9, but we still use the V8 register
+// order.
+target_ulong helper_rdcwp(void)
+{
+ return GET_CWP64(env);
+}
-void do_popc()
+void helper_wrcwp(target_ulong new_cwp)
{
- T0 = ctpop64(T1);
+ PUT_CWP64(env, new_cwp);
+}
+
+// This function uses non-native bit order
+#define GET_FIELD(X, FROM, TO) \
+ ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
+
+// This function uses the order in the manuals, i.e. bit 0 is 2^0
+#define GET_FIELD_SP(X, FROM, TO) \
+ GET_FIELD(X, 63 - (TO), 63 - (FROM))
+
+target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
+{
+ return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
+ (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
+ (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
+ (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
+ (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
+ (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
+ (((pixel_addr >> 55) & 1) << 4) |
+ (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
+ GET_FIELD_SP(pixel_addr, 11, 12);
+}
+
+target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
+{
+ uint64_t tmp;
+
+ tmp = addr + offset;
+ env->gsr &= ~7ULL;
+ env->gsr |= tmp & 7ULL;
+ return tmp & ~7ULL;
+}
+
+target_ulong helper_popc(target_ulong val)
+{
+ return ctpop64(val);
}
static inline uint64_t *get_gregset(uint64_t pstate)
env->pstate = new_pstate;
}
-void do_wrpstate(void)
+void helper_wrpstate(target_ulong new_state)
{
- change_pstate(T0 & 0xf3f);
+ change_pstate(new_state & 0xf3f);
}
-void do_done(void)
+void helper_done(void)
{
env->tl--;
- env->pc = env->tnpc[env->tl];
- env->npc = env->tnpc[env->tl] + 4;
- PUT_CCR(env, env->tstate[env->tl] >> 32);
- env->asi = (env->tstate[env->tl] >> 24) & 0xff;
- change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
- PUT_CWP64(env, env->tstate[env->tl] & 0xff);
+ env->tsptr = &env->ts[env->tl];
+ env->pc = env->tsptr->tpc;
+ env->npc = env->tsptr->tnpc + 4;
+ PUT_CCR(env, env->tsptr->tstate >> 32);
+ env->asi = (env->tsptr->tstate >> 24) & 0xff;
+ change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
+ PUT_CWP64(env, env->tsptr->tstate & 0xff);
}
-void do_retry(void)
+void helper_retry(void)
{
env->tl--;
- env->pc = env->tpc[env->tl];
- env->npc = env->tnpc[env->tl];
- PUT_CCR(env, env->tstate[env->tl] >> 32);
- env->asi = (env->tstate[env->tl] >> 24) & 0xff;
- change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
- PUT_CWP64(env, env->tstate[env->tl] & 0xff);
+ env->tsptr = &env->ts[env->tl];
+ env->pc = env->tsptr->tpc;
+ env->npc = env->tsptr->tnpc;
+ PUT_CCR(env, env->tsptr->tstate >> 32);
+ env->asi = (env->tsptr->tstate >> 24) & 0xff;
+ change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
+ PUT_CWP64(env, env->tsptr->tstate & 0xff);
}
#endif
}
#ifdef TARGET_SPARC64
+#ifdef DEBUG_PCALL
+static const char * const excp_names[0x50] = {
+ [TT_TFAULT] = "Instruction Access Fault",
+ [TT_TMISS] = "Instruction Access MMU Miss",
+ [TT_CODE_ACCESS] = "Instruction Access Error",
+ [TT_ILL_INSN] = "Illegal Instruction",
+ [TT_PRIV_INSN] = "Privileged Instruction",
+ [TT_NFPU_INSN] = "FPU Disabled",
+ [TT_FP_EXCP] = "FPU Exception",
+ [TT_TOVF] = "Tag Overflow",
+ [TT_CLRWIN] = "Clean Windows",
+ [TT_DIV_ZERO] = "Division By Zero",
+ [TT_DFAULT] = "Data Access Fault",
+ [TT_DMISS] = "Data Access MMU Miss",
+ [TT_DATA_ACCESS] = "Data Access Error",
+ [TT_DPROT] = "Data Protection Error",
+ [TT_UNALIGNED] = "Unaligned Memory Access",
+ [TT_PRIV_ACT] = "Privileged Action",
+ [TT_EXTINT | 0x1] = "External Interrupt 1",
+ [TT_EXTINT | 0x2] = "External Interrupt 2",
+ [TT_EXTINT | 0x3] = "External Interrupt 3",
+ [TT_EXTINT | 0x4] = "External Interrupt 4",
+ [TT_EXTINT | 0x5] = "External Interrupt 5",
+ [TT_EXTINT | 0x6] = "External Interrupt 6",
+ [TT_EXTINT | 0x7] = "External Interrupt 7",
+ [TT_EXTINT | 0x8] = "External Interrupt 8",
+ [TT_EXTINT | 0x9] = "External Interrupt 9",
+ [TT_EXTINT | 0xa] = "External Interrupt 10",
+ [TT_EXTINT | 0xb] = "External Interrupt 11",
+ [TT_EXTINT | 0xc] = "External Interrupt 12",
+ [TT_EXTINT | 0xd] = "External Interrupt 13",
+ [TT_EXTINT | 0xe] = "External Interrupt 14",
+ [TT_EXTINT | 0xf] = "External Interrupt 15",
+};
+#endif
+
void do_interrupt(int intno)
{
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_INT) {
static int count;
- fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
- count, intno,
+ const char *name;
+
+ if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
+ name = "Unknown";
+ else if (intno >= 0x100)
+ name = "Trap Instruction";
+ else if (intno >= 0xc0)
+ name = "Window Fill";
+ else if (intno >= 0x80)
+ name = "Window Spill";
+ else {
+ name = excp_names[intno];
+ if (!name)
+ name = "Unknown";
+ }
+
+ fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
+ " SP=%016" PRIx64 "\n",
+ count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
cpu_dump_state(env, logfile, fprintf, 0);
return;
}
#endif
- env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
- ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
- env->tpc[env->tl] = env->pc;
- env->tnpc[env->tl] = env->npc;
- env->tt[env->tl] = intno;
+ env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
+ ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
+ GET_CWP64(env);
+ env->tsptr->tpc = env->pc;
+ env->tsptr->tnpc = env->npc;
+ env->tsptr->tt = intno;
change_pstate(PS_PEF | PS_PRIV | PS_AG);
if (intno == TT_CLRWIN)
if (env->tl != MAXTL)
env->tl++;
}
+ env->tsptr = &env->ts[env->tl];
env->pc = env->tbr;
env->npc = env->pc + 4;
env->exception_index = 0;
}
#else
+#ifdef DEBUG_PCALL
+static const char * const excp_names[0x80] = {
+ [TT_TFAULT] = "Instruction Access Fault",
+ [TT_ILL_INSN] = "Illegal Instruction",
+ [TT_PRIV_INSN] = "Privileged Instruction",
+ [TT_NFPU_INSN] = "FPU Disabled",
+ [TT_WIN_OVF] = "Window Overflow",
+ [TT_WIN_UNF] = "Window Underflow",
+ [TT_UNALIGNED] = "Unaligned Memory Access",
+ [TT_FP_EXCP] = "FPU Exception",
+ [TT_DFAULT] = "Data Access Fault",
+ [TT_TOVF] = "Tag Overflow",
+ [TT_EXTINT | 0x1] = "External Interrupt 1",
+ [TT_EXTINT | 0x2] = "External Interrupt 2",
+ [TT_EXTINT | 0x3] = "External Interrupt 3",
+ [TT_EXTINT | 0x4] = "External Interrupt 4",
+ [TT_EXTINT | 0x5] = "External Interrupt 5",
+ [TT_EXTINT | 0x6] = "External Interrupt 6",
+ [TT_EXTINT | 0x7] = "External Interrupt 7",
+ [TT_EXTINT | 0x8] = "External Interrupt 8",
+ [TT_EXTINT | 0x9] = "External Interrupt 9",
+ [TT_EXTINT | 0xa] = "External Interrupt 10",
+ [TT_EXTINT | 0xb] = "External Interrupt 11",
+ [TT_EXTINT | 0xc] = "External Interrupt 12",
+ [TT_EXTINT | 0xd] = "External Interrupt 13",
+ [TT_EXTINT | 0xe] = "External Interrupt 14",
+ [TT_EXTINT | 0xf] = "External Interrupt 15",
+ [TT_TOVF] = "Tag Overflow",
+ [TT_CODE_ACCESS] = "Instruction Access Error",
+ [TT_DATA_ACCESS] = "Data Access Error",
+ [TT_DIV_ZERO] = "Division By Zero",
+ [TT_NCP_INSN] = "Coprocessor Disabled",
+};
+#endif
+
void do_interrupt(int intno)
{
int cwp;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_INT) {
static int count;
- fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
- count, intno,
+ const char *name;
+
+ if (intno < 0 || intno >= 0x100)
+ name = "Unknown";
+ else if (intno >= 0x80)
+ name = "Trap Instruction";
+ else {
+ name = excp_names[intno];
+ if (!name)
+ name = "Unknown";
+ }
+
+ fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
+ count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
cpu_dump_state(env, logfile, fprintf, 0);
generated code */
saved_env = env;
env = cpu_single_env;
+#ifdef DEBUG_UNASSIGNED
+ if (is_asi)
+ printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
+ TARGET_FMT_lx "\n",
+ is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
+ env->pc);
+ else
+ printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
+ TARGET_FMT_lx "\n",
+ is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
+#endif
if (env->mmuregs[3]) /* Fault status register */
env->mmuregs[3] = 1; /* overflow (not read before another fault) */
if (is_asi)
env->mmuregs[3] |= (5 << 2) | 2;
env->mmuregs[4] = addr; /* Fault address register */
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
-#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
- "\n", addr, env->pc);
-#endif
if (is_exec)
raise_exception(TT_CODE_ACCESS);
else
}
#endif
-#ifdef TARGET_SPARC64
-void do_tick_set_count(void *opaque, uint64_t count)
-{
-#if !defined(CONFIG_USER_ONLY)
- ptimer_set_count(opaque, -count);
-#endif
-}
-
-uint64_t do_tick_get_count(void *opaque)
-{
-#if !defined(CONFIG_USER_ONLY)
- return -ptimer_get_count(opaque);
-#else
- return 0;
-#endif
-}
-
-void do_tick_set_limit(void *opaque, uint64_t limit)
-{
-#if !defined(CONFIG_USER_ONLY)
- ptimer_set_limit(opaque, -limit, 0);
-#endif
-}
-#endif
projects / qemu.git / blobdiff