* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "cpu.h"
#include "mmu.h"
#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
//#define CRIS_HELPER_DEBUG
#if defined(CONFIG_USER_ONLY)
-void do_interrupt(CPUCRISState *env)
+void cris_cpu_do_interrupt(CPUState *cs)
{
- env->exception_index = -1;
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
+
+ cs->exception_index = -1;
env->pregs[PR_ERP] = env->pc;
}
-int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
+void crisv10_cpu_do_interrupt(CPUState *cs)
+{
+ cris_cpu_do_interrupt(cs);
+}
+
+int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- env->exception_index = 0xaa;
- env->pregs[PR_EDA] = address;
- cpu_dump_state(env, stderr, fprintf, 0);
+ CRISCPU *cpu = CRIS_CPU(cs);
+
+ cs->exception_index = 0xaa;
+ cpu->env.pregs[PR_EDA] = address;
+ cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
}
env->pregs[PR_CCS] = ccs;
}
-int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
+int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
struct cris_mmu_result res;
int prot, miss;
int r = -1;
target_ulong phy;
- D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
+ qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
+ __func__, address, env->pc, rw);
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
rw, mmu_idx, 0);
if (miss) {
- if (env->exception_index == EXCP_BUSFAULT) {
- cpu_abort(env,
+ if (cs->exception_index == EXCP_BUSFAULT) {
+ cpu_abort(cs,
"CRIS: Illegal recursive bus fault."
- "addr=%x rw=%d\n",
+ "addr=%" VADDR_PRIx " rw=%d\n",
address, rw);
}
env->pregs[PR_EDA] = address;
- env->exception_index = EXCP_BUSFAULT;
+ cs->exception_index = EXCP_BUSFAULT;
env->fault_vector = res.bf_vec;
r = 1;
} else {
*/
phy = res.phy & ~0x80000000;
prot = res.prot;
- tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
if (r > 0) {
- D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
- __func__, r, cpu->interrupt_request, address, res.phy,
- res.bf_vec, env->pc);
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
+ " pc=%x\n", __func__, r, cs->interrupt_request, address,
+ res.phy, res.bf_vec, env->pc);
}
return r;
}
-static void do_interruptv10(CPUCRISState *env)
+void crisv10_cpu_do_interrupt(CPUState *cs)
{
- D(CPUState *cs = CPU(cris_env_get_cpu(env)));
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
- env->exception_index,
+ cs->exception_index,
cs->interrupt_request);
+ if (env->dslot) {
+ /* CRISv10 never takes interrupts while in a delay-slot. */
+ cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
+ }
+
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
ERP should point to the insn following the brk. */
break;
case EXCP_BUSFAULT:
- cpu_abort(env, "Unhandled busfault");
+ cpu_abort(cs, "Unhandled busfault");
break;
default:
env->pregs[PR_ERP]);
}
-void do_interrupt(CPUCRISState *env)
+void cris_cpu_do_interrupt(CPUState *cs)
{
- D(CPUState *cs = CPU(cris_env_get_cpu(env)));
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
int ex_vec = -1;
- if (env->pregs[PR_VR] < 32) {
- return do_interruptv10(env);
- }
-
D_LOG("exception index=%d interrupt_req=%d\n",
- env->exception_index,
+ cs->exception_index,
cs->interrupt_request);
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
ERP should point to the insn following the brk. */
/* Clear the excption_index to avoid spurios hw_aborts for recursive
bus faults. */
- env->exception_index = -1;
+ cs->exception_index = -1;
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
env->pregs[PR_ERP]);
}
-hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
+hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
uint32_t phy = addr;
struct cris_mmu_result res;
int miss;
- miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
+ miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
/* If D TLB misses, try I TLB. */
if (miss) {
- miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
+ miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
}
if (!miss) {
return phy;
}
#endif
+
+bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
+ bool ret = false;
+
+ if (interrupt_request & CPU_INTERRUPT_HARD
+ && (env->pregs[PR_CCS] & I_FLAG)
+ && !env->locked_irq) {
+ cs->exception_index = EXCP_IRQ;
+ cc->do_interrupt(cs);
+ ret = true;
+ }
+ if (interrupt_request & CPU_INTERRUPT_NMI) {
+ unsigned int m_flag_archval;
+ if (env->pregs[PR_VR] < 32) {
+ m_flag_archval = M_FLAG_V10;
+ } else {
+ m_flag_archval = M_FLAG_V32;
+ }
+ if ((env->pregs[PR_CCS] & m_flag_archval)) {
+ cs->exception_index = EXCP_NMI;
+ cc->do_interrupt(cs);
+ ret = true;
+ }
+ }
+
+ return ret;
+}
projects / qemu.git / blobdiff