*
* This code is licensed under the GNU GPL v2.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
*/
/*
#include "mips.h"
#include "pci_host.h"
#include "sysemu.h"
+#include "exec-memory.h"
//#define DEBUG_BONITO
} boncop;
/* Bonito registers */
- target_phys_addr_t bonito_reg_start;
- target_phys_addr_t bonito_reg_length;
- int bonito_reg_handle;
-
- target_phys_addr_t bonito_pciconf_start;
- target_phys_addr_t bonito_pciconf_length;
- int bonito_pciconf_handle;
-
- target_phys_addr_t bonito_spciconf_start;
- target_phys_addr_t bonito_spciconf_length;
- int bonito_spciconf_handle;
+ MemoryRegion iomem;
+ MemoryRegion iomem_ldma;
+ MemoryRegion iomem_cop;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
target_phys_addr_t bonito_localio_length;
int bonito_localio_handle;
- target_phys_addr_t bonito_ldma_start;
- target_phys_addr_t bonito_ldma_length;
- int bonito_ldma_handle;
-
- target_phys_addr_t bonito_cop_start;
- target_phys_addr_t bonito_cop_length;
- int bonito_cop_handle;
-
} PCIBonitoState;
PCIBonitoState * bonito_state;
-static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void bonito_writel(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
saddr = (addr - BONITO_REGBASE) >> 2;
- DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x \n", addr, val, saddr);
+ DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
case BONITO_IODEVCFG:
break;
case BONITO_INTEN:
case BONITO_INTISR:
- DPRINTF("write to readonly bonito register %x \n", saddr);
+ DPRINTF("write to readonly bonito register %x\n", saddr);
break;
default:
- DPRINTF("write to unknown bonito register %x \n", saddr);
+ DPRINTF("write to unknown bonito register %x\n", saddr);
break;
}
}
-static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
saddr = (addr - BONITO_REGBASE) >> 2;
- DPRINTF("bonito_readl "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
switch (saddr) {
case BONITO_INTISR:
return s->regs[saddr];
}
}
-static CPUWriteMemoryFunc * const bonito_write[] = {
- NULL,
- NULL,
- bonito_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_read[] = {
- NULL,
- NULL,
- bonito_readl,
+static const MemoryRegionOps bonito_ops = {
+ .read = bonito_readl,
+ .write = bonito_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
- DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
s->dev.config_write(&s->dev, addr, val, 4);
}
-static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PCIBonitoState *s = opaque;
}
/* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
-static CPUWriteMemoryFunc * const bonito_pciconf_write[] = {
- NULL,
- NULL,
- bonito_pciconf_writel,
-};
-static CPUReadMemoryFunc * const bonito_pciconf_read[] = {
- NULL,
- NULL,
- bonito_pciconf_readl,
+static const MemoryRegionOps bonito_pciconf_ops = {
+ .read = bonito_pciconf_readl,
+ .write = bonito_pciconf_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
}
static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
-static CPUWriteMemoryFunc * const bonito_ldma_write[] = {
- NULL,
- NULL,
- bonito_ldma_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_ldma_read[] = {
- NULL,
- NULL,
- bonito_ldma_readl,
+static const MemoryRegionOps bonito_ldma_ops = {
+ .read = bonito_ldma_readl,
+ .write = bonito_ldma_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
}
static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
-static CPUWriteMemoryFunc * const bonito_cop_write[] = {
- NULL,
- NULL,
- bonito_cop_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_cop_read[] = {
- NULL,
- NULL,
- bonito_cop_readl,
+static const MemoryRegionOps bonito_cop_ops = {
+ .read = bonito_cop_readl,
+ .write = bonito_cop_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
exit(1);
}
pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno);
- DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d \n",
+ DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno);
return pciaddr;
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr&0x1)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr&0x3)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
assert((addr&0x1)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
assert((addr&0x3) == 0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
}
/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
-static CPUWriteMemoryFunc * const bonito_spciconf_write[] = {
- bonito_spciconf_writeb,
- bonito_spciconf_writew,
- bonito_spciconf_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_spciconf_read[] = {
- bonito_spciconf_readb,
- bonito_spciconf_readw,
- bonito_spciconf_readl,
+static const MemoryRegionOps bonito_spciconf_ops = {
+ .old_mmio = {
+ .read = {
+ bonito_spciconf_readb,
+ bonito_spciconf_readw,
+ bonito_spciconf_readl,
+ },
+ .write = {
+ bonito_spciconf_writeb,
+ bonito_spciconf_writew,
+ bonito_spciconf_writel,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#define BONITO_IRQ_BASE 32
static int bonito_initfn(PCIDevice *dev)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
+ SysBusDevice *sysbus = &s->pcihost->busdev;
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
- pci_config_set_vendor_id(dev->config, 0xdf53);
- pci_config_set_device_id(dev->config, 0x00d5);
- pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
pci_config_set_prog_interface(dev->config, 0x00);
- pci_config_set_revision(dev->config, 0x01);
/* set the north bridge register mapping */
- s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
- s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
- cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
- s->bonito_reg_handle);
+ memory_region_init_io(&s->iomem, &bonito_ops, s,
+ "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
+ sysbus_init_mmio(sysbus, &s->iomem);
+ sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
/* set the north bridge pci configure mapping */
- s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
- bonito_pciconf_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
- s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
- cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
- s->bonito_pciconf_handle);
+ memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s,
+ "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
+ sysbus_init_mmio(sysbus, &s->pcihost->conf_mem);
+ sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
/* set the south bridge pci configure mapping */
- s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
- bonito_spciconf_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
- s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
- cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
- s->bonito_spciconf_handle);
-
- s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
- bonito_ldma_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_ldma_start = 0xbfe00200;
- s->bonito_ldma_length = 0x100;
- cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
- s->bonito_ldma_handle);
-
- s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
- bonito_cop_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_cop_start = 0xbfe00300;
- s->bonito_cop_length = 0x100;
- cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
- s->bonito_cop_handle);
+ memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s,
+ "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
+ sysbus_init_mmio(sysbus, &s->pcihost->data_mem);
+ sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
+
+ memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s,
+ "ldma", 0x100);
+ sysbus_init_mmio(sysbus, &s->iomem_ldma);
+ sysbus_mmio_map(sysbus, 3, 0xbfe00200);
+
+ memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s,
+ "cop", 0x100);
+ sysbus_init_mmio(sysbus, &s->iomem_cop);
+ sysbus_mmio_map(sysbus, 4, 0xbfe00300);
/* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
s->bonito_pciio_start = BONITO_PCIIO_BASE;
s->bonito_pciio_length = BONITO_PCIIO_SIZE;
isa_mem_base = s->bonito_pciio_start;
- isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length, 0);
+ isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length);
/* add pci local io mapping */
s->bonito_localio_start = BONITO_DEV_BASE;
s->bonito_localio_length = BONITO_DEV_SIZE;
- isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length, 0);
+ isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length);
/* set the default value of north bridge pci config */
pci_set_word(dev->config + PCI_COMMAND, 0x0000);
dev = qdev_create(NULL, "Bonito-pcihost");
pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
- pci_bonito_map_irq, pic, 0x28, 32);
+ pci_bonito_map_irq, pic, get_system_memory(),
+ get_system_io(),
+ 0x28, 32);
pcihost->bus = b;
qdev_init_nofail(dev);
- d = pci_create_simple(b, PCI_DEVFN(0, 0), "Bonito");
+ /* set the pcihost pointer before bonito_initfn is called */
+ d = pci_create(b, PCI_DEVFN(0, 0), "Bonito");
s = DO_UPCAST(PCIBonitoState, dev, d);
s->pcihost = pcihost;
bonito_state = s;
+ qdev_init_nofail(&d->qdev);
return b;
}
-static PCIDeviceInfo bonito_info = {
- .qdev.name = "Bonito",
- .qdev.desc = "Host bridge",
- .qdev.size = sizeof(PCIBonitoState),
- .qdev.vmsd = &vmstate_bonito,
- .qdev.no_user = 1,
- .init = bonito_initfn,
+static void bonito_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->init = bonito_initfn;
+ k->vendor_id = 0xdf53;
+ k->device_id = 0x00d5;
+ k->revision = 0x01;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ dc->desc = "Host bridge";
+ dc->no_user = 1;
+ dc->vmsd = &vmstate_bonito;
+}
+
+static TypeInfo bonito_info = {
+ .name = "Bonito",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PCIBonitoState),
+ .class_init = bonito_class_init,
};
-static SysBusDeviceInfo bonito_pcihost_info = {
- .init = bonito_pcihost_initfn,
- .qdev.name = "Bonito-pcihost",
- .qdev.size = sizeof(BonitoState),
- .qdev.no_user = 1,
+static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = bonito_pcihost_initfn;
+ dc->no_user = 1;
+}
+
+static TypeInfo bonito_pcihost_info = {
+ .name = "Bonito-pcihost",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BonitoState),
+ .class_init = bonito_pcihost_class_init,
};
-static void bonito_register(void)
+static void bonito_register_types(void)
{
- sysbus_register_withprop(&bonito_pcihost_info);
- pci_qdev_register(&bonito_info);
+ type_register_static(&bonito_pcihost_info);
+ type_register_static(&bonito_info);
}
-device_init(bonito_register);
+
+type_init(bonito_register_types)
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