* Copyright (c) 2007 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
-#include "hw.h"
+#include "sysbus.h"
+#include "ssi.h"
#include "primecell.h"
//#define DEBUG_PL022 1
#ifdef DEBUG_PL022
-#define DPRINTF(fmt, args...) \
-do { printf("pl022: " fmt , ##args); } while (0)
-#define BADF(fmt, args...) \
-do { fprintf(stderr, "pl022: error: " fmt , ##args); exit(1);} while (0)
+#define DPRINTF(fmt, ...) \
+do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
-#define DPRINTF(fmt, args...) do {} while(0)
-#define BADF(fmt, args...) \
-do { fprintf(stderr, "pl022: error: " fmt , ##args);} while (0)
+#define DPRINTF(fmt, ...) do {} while(0)
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
#endif
#define PL022_CR1_LBM 0x01
#define PL022_INT_TX 0x08
typedef struct {
- uint32_t base;
+ SysBusDevice busdev;
uint32_t cr0;
uint32_t cr1;
uint32_t bitmask;
uint16_t tx_fifo[8];
uint16_t rx_fifo[8];
qemu_irq irq;
- int (*xfer_cb)(void *, int);
- void *opaque;
+ SSIBus *ssi;
} pl022_state;
static const unsigned char pl022_id[8] =
val = s->tx_fifo[i];
if (s->cr1 & PL022_CR1_LBM) {
/* Loopback mode. */
- } else if (s->xfer_cb) {
- val = s->xfer_cb(s->opaque, val);
} else {
- val = 0;
+ val = ssi_transfer(s->ssi, val);
}
s->rx_fifo[o] = val & s->bitmask;
i = (i + 1) & 7;
pl022_state *s = (pl022_state *)opaque;
int val;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl022_id[(offset - 0xfe0) >> 2];
}
/* Not implemented. */
return 0;
default:
- cpu_abort (cpu_single_env, "pl022_read: Bad offset %x\n",
- (int)offset);
+ hw_error("pl022_read: Bad offset %x\n", (int)offset);
return 0;
}
}
{
pl022_state *s = (pl022_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* CR0 */
s->cr0 = value;
pl022_update(s);
break;
case 0x20: /* DMACR */
- if (value)
- cpu_abort (cpu_single_env, "pl022: DMA not implemented\n");
+ if (value) {
+ hw_error("pl022: DMA not implemented\n");
+ }
break;
default:
- cpu_abort (cpu_single_env, "pl022_write: Bad offset %x\n",
- (int)offset);
+ hw_error("pl022_write: Bad offset %x\n", (int)offset);
}
}
s->sr = PL022_SR_TFE | PL022_SR_TNF;
}
-static CPUReadMemoryFunc *pl022_readfn[] = {
+static CPUReadMemoryFunc * const pl022_readfn[] = {
pl022_read,
pl022_read,
pl022_read
};
-static CPUWriteMemoryFunc *pl022_writefn[] = {
+static CPUWriteMemoryFunc * const pl022_writefn[] = {
pl022_write,
pl022_write,
pl022_write
};
-static void pl022_save(QEMUFile *f, void *opaque)
-{
- pl022_state *s = (pl022_state *)opaque;
- int i;
-
- qemu_put_be32(f, s->cr0);
- qemu_put_be32(f, s->cr1);
- qemu_put_be32(f, s->bitmask);
- qemu_put_be32(f, s->sr);
- qemu_put_be32(f, s->cpsr);
- qemu_put_be32(f, s->is);
- qemu_put_be32(f, s->im);
- qemu_put_be32(f, s->tx_fifo_head);
- qemu_put_be32(f, s->rx_fifo_head);
- qemu_put_be32(f, s->tx_fifo_len);
- qemu_put_be32(f, s->rx_fifo_len);
- for (i = 0; i < 8; i++) {
- qemu_put_be16(f, s->tx_fifo[i]);
- qemu_put_be16(f, s->rx_fifo[i]);
+static const VMStateDescription vmstate_pl022 = {
+ .name = "pl022_ssp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(cr0, pl022_state),
+ VMSTATE_UINT32(cr1, pl022_state),
+ VMSTATE_UINT32(bitmask, pl022_state),
+ VMSTATE_UINT32(sr, pl022_state),
+ VMSTATE_UINT32(cpsr, pl022_state),
+ VMSTATE_UINT32(is, pl022_state),
+ VMSTATE_UINT32(im, pl022_state),
+ VMSTATE_INT32(tx_fifo_head, pl022_state),
+ VMSTATE_INT32(rx_fifo_head, pl022_state),
+ VMSTATE_INT32(tx_fifo_len, pl022_state),
+ VMSTATE_INT32(rx_fifo_len, pl022_state),
+ VMSTATE_UINT16(tx_fifo[0], pl022_state),
+ VMSTATE_UINT16(rx_fifo[0], pl022_state),
+ VMSTATE_UINT16(tx_fifo[1], pl022_state),
+ VMSTATE_UINT16(rx_fifo[1], pl022_state),
+ VMSTATE_UINT16(tx_fifo[2], pl022_state),
+ VMSTATE_UINT16(rx_fifo[2], pl022_state),
+ VMSTATE_UINT16(tx_fifo[3], pl022_state),
+ VMSTATE_UINT16(rx_fifo[3], pl022_state),
+ VMSTATE_UINT16(tx_fifo[4], pl022_state),
+ VMSTATE_UINT16(rx_fifo[4], pl022_state),
+ VMSTATE_UINT16(tx_fifo[5], pl022_state),
+ VMSTATE_UINT16(rx_fifo[5], pl022_state),
+ VMSTATE_UINT16(tx_fifo[6], pl022_state),
+ VMSTATE_UINT16(rx_fifo[6], pl022_state),
+ VMSTATE_UINT16(tx_fifo[7], pl022_state),
+ VMSTATE_UINT16(rx_fifo[7], pl022_state),
+ VMSTATE_END_OF_LIST()
}
-}
+};
-static int pl022_load(QEMUFile *f, void *opaque, int version_id)
+static int pl022_init(SysBusDevice *dev)
{
- pl022_state *s = (pl022_state *)opaque;
- int i;
-
- if (version_id != 1)
- return -EINVAL;
-
- s->cr0 = qemu_get_be32(f);
- s->cr1 = qemu_get_be32(f);
- s->bitmask = qemu_get_be32(f);
- s->sr = qemu_get_be32(f);
- s->cpsr = qemu_get_be32(f);
- s->is = qemu_get_be32(f);
- s->im = qemu_get_be32(f);
- s->tx_fifo_head = qemu_get_be32(f);
- s->rx_fifo_head = qemu_get_be32(f);
- s->tx_fifo_len = qemu_get_be32(f);
- s->rx_fifo_len = qemu_get_be32(f);
- for (i = 0; i < 8; i++) {
- s->tx_fifo[i] = qemu_get_be16(f);
- s->rx_fifo[i] = qemu_get_be16(f);
- }
+ pl022_state *s = FROM_SYSBUS(pl022_state, dev);
+ int iomemtype;
+ iomemtype = cpu_register_io_memory(pl022_readfn,
+ pl022_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, 0x1000, iomemtype);
+ sysbus_init_irq(dev, &s->irq);
+ s->ssi = ssi_create_bus(&dev->qdev, "ssi");
+ pl022_reset(s);
+ vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
return 0;
}
-void pl022_init(uint32_t base, qemu_irq irq, int (*xfer_cb)(void *, int),
- void * opaque)
+static void pl022_register_devices(void)
{
- int iomemtype;
- pl022_state *s;
-
- s = (pl022_state *)qemu_mallocz(sizeof(pl022_state));
- iomemtype = cpu_register_io_memory(0, pl022_readfn,
- pl022_writefn, s);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
- s->irq = irq;
- s->xfer_cb = xfer_cb;
- s->opaque = opaque;
- pl022_reset(s);
- register_savevm("pl022_ssp", -1, 1, pl022_save, pl022_load, s);
+ sysbus_register_dev("pl022", sizeof(pl022_state), pl022_init);
}
-
+device_init(pl022_register_devices)
projects / qemu.git / blobdiff