//#define DEBUG_GIC
#ifdef DEBUG_GIC
-#define DPRINTF(fmt, args...) \
-do { printf("arm_gic: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) \
+do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define DPRINTF(fmt, args...) do {} while(0)
+#define DPRINTF(fmt, ...) do {} while(0)
#endif
#ifdef NVIC
static const uint8_t gic_id[] =
{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
-#define GIC_DIST_OFFSET 0
/* The NVIC has 16 internal vectors. However these are not exposed
through the normal GIC interface. */
#define GIC_BASE_IRQ 32
#else
static const uint8_t gic_id[] =
{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
-#define GIC_DIST_OFFSET 0x1000
#define GIC_BASE_IRQ 0
#endif
+#define FROM_SYSBUSGIC(type, dev) \
+ DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
+
typedef struct gic_irq_state
{
/* ??? The documentation seems to imply the enable bits are global, even
unsigned enabled:1;
unsigned pending:NCPU;
unsigned active:NCPU;
- unsigned level:1;
+ unsigned level:NCPU;
unsigned model:1; /* 0 = N:N, 1 = 1:N */
unsigned trigger:1; /* nonzero = edge triggered. */
} gic_irq_state;
#define ALL_CPU_MASK ((1 << NCPU) - 1)
+#if NCPU > 1
+#define NUM_CPU(s) ((s)->num_cpu)
+#else
+#define NUM_CPU(s) 1
+#endif
#define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
#define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
typedef struct gic_state
{
- uint32_t base;
+ SysBusDevice busdev;
qemu_irq parent_irq[NCPU];
int enabled;
int cpu_enabled[NCPU];
int running_priority[NCPU];
int current_pending[NCPU];
- qemu_irq *in;
-#ifdef NVIC
- void *nvic;
+#if NCPU > 1
+ int num_cpu;
#endif
+
+ int iomemtype;
} gic_state;
/* TODO: Many places that call this routine could be optimized. */
int cpu;
int cm;
- for (cpu = 0; cpu < NCPU; cpu++) {
+ for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
cm = 1 << cpu;
s->current_pending[cpu] = 1023;
if (!s->enabled || !s->cpu_enabled[cpu]) {
cpu = gic_get_current_cpu();
cm = 1 << cpu;
- offset -= s->base + GIC_DIST_OFFSET;
if (offset < 0x100) {
#ifndef NVIC
if (offset == 0)
return s->enabled;
if (offset == 4)
- return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5);
+ return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
if (offset < 0x08)
return 0;
#endif
}
return res;
bad_reg:
- cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset);
+ hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
return 0;
}
#ifdef NVIC
gic_state *s = (gic_state *)opaque;
uint32_t addr;
- addr = offset - s->base;
+ addr = offset;
if (addr < 0x100 || addr > 0xd00)
- return nvic_readl(s->nvic, addr);
+ return nvic_readl(s, addr);
#endif
val = gic_dist_readw(opaque, offset);
val |= gic_dist_readw(opaque, offset + 2) << 16;
int cpu;
cpu = gic_get_current_cpu();
- offset -= s->base + GIC_DIST_OFFSET;
if (offset < 0x100) {
#ifdef NVIC
goto bad_reg;
gic_update(s);
return;
bad_reg:
- cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset);
+ hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
gic_state *s = (gic_state *)opaque;
#ifdef NVIC
uint32_t addr;
- addr = offset - s->base;
+ addr = offset;
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
- nvic_writel(s->nvic, addr, value);
+ nvic_writel(s, addr, value);
return;
}
#endif
- if (offset - s->base == GIC_DIST_OFFSET + 0xf00) {
+ if (offset == 0xf00) {
int cpu;
int irq;
int mask;
gic_dist_writew(opaque, offset + 2, value >> 16);
}
-static CPUReadMemoryFunc *gic_dist_readfn[] = {
+static CPUReadMemoryFunc * const gic_dist_readfn[] = {
gic_dist_readb,
gic_dist_readw,
gic_dist_readl
};
-static CPUWriteMemoryFunc *gic_dist_writefn[] = {
+static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
gic_dist_writeb,
gic_dist_writew,
gic_dist_writel
case 0x18: /* Highest Pending Interrupt */
return s->current_pending[cpu];
default:
- cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
- (int)offset);
+ hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
return 0;
}
}
switch (offset) {
case 0x00: /* Control */
s->cpu_enabled[cpu] = (value & 1);
- DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis");
+ DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
break;
case 0x04: /* Priority mask */
s->priority_mask[cpu] = (value & 0xff);
case 0x10: /* End Of Interrupt */
return gic_complete_irq(s, cpu, value & 0x3ff);
default:
- cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
- (int)offset);
+ hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
return;
}
gic_update(s);
{
int i;
memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
- for (i = 0 ; i < NCPU; i++) {
+ for (i = 0 ; i < NUM_CPU(s); i++) {
s->priority_mask[i] = 0xf0;
s->current_pending[i] = 1023;
s->running_irq[i] = 1023;
int j;
qemu_put_be32(f, s->enabled);
- for (i = 0; i < NCPU; i++) {
+ for (i = 0; i < NUM_CPU(s); i++) {
qemu_put_be32(f, s->cpu_enabled[i]);
#ifndef NVIC
qemu_put_be32(f, s->irq_target[i]);
return -EINVAL;
s->enabled = qemu_get_be32(f);
- for (i = 0; i < NCPU; i++) {
+ for (i = 0; i < NUM_CPU(s); i++) {
s->cpu_enabled[i] = qemu_get_be32(f);
#ifndef NVIC
s->irq_target[i] = qemu_get_be32(f);
return 0;
}
-static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq)
+#if NCPU > 1
+static void gic_init(gic_state *s, int num_cpu)
+#else
+static void gic_init(gic_state *s)
+#endif
{
- gic_state *s;
- int iomemtype;
int i;
- s = (gic_state *)qemu_mallocz(sizeof(gic_state));
- if (!s)
- return NULL;
- s->in = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ);
- for (i = 0; i < NCPU; i++) {
- s->parent_irq[i] = parent_irq[i];
+#if NCPU > 1
+ s->num_cpu = num_cpu;
+#endif
+ qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
+ for (i = 0; i < NUM_CPU(s); i++) {
+ sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
- iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
- gic_dist_writefn, s);
- cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000,
- iomemtype);
- s->base = base;
+ s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
+ gic_dist_writefn, s);
gic_reset(s);
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
- return s;
}
projects / qemu.git / blobdiff