#include "exec/address-spaces.h"
#include "elf.h"
+#include <libfdt.h>
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_u_memmap[] = {
[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0x2000 },
+ [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
-static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
-{
- int i;
- for (i = 0; i < (len >> 2); i++) {
- stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
- }
-}
-
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
+#define GEM_REVISION 0x10070109
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
- error_report("qemu: could not load kernel '%s'", kernel_filename);
+ 0, EM_RISCV, 1, 0) < 0) {
+ error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
return kernel_entry;
int cpu;
uint32_t *cells;
char *nodename;
- uint32_t plic_phandle;
+ char ethclk_names[] = "pclk\0hclk\0tx_clk";
+ uint32_t plic_phandle, ethclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
qemu_fdt_add_subnode(fdt, "/soc");
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
- qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
g_free(nodename);
qemu_fdt_add_subnode(fdt, "/cpus");
- qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
+ SIFIVE_CLINT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
- for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
+ for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
- char *isa = riscv_isa_string(&s->soc.harts[cpu]);
+ char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_CLOCK_FREQ);
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
g_free(nodename);
}
- cells = g_new0(uint32_t, s->soc.num_harts * 4);
- for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
+ cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
+ for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
nodename =
g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
0x0, memmap[SIFIVE_U_CLINT].base,
0x0, memmap[SIFIVE_U_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
- cells, s->soc.num_harts * sizeof(uint32_t) * 4);
+ cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
g_free(cells);
g_free(nodename);
- cells = g_new0(uint32_t, s->soc.num_harts * 4);
- for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
+ cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
+ for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
nodename =
g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
- cells, s->soc.num_harts * sizeof(uint32_t) * 4);
+ cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_PLIC].base,
0x0, memmap[SIFIVE_U_PLIC].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
+ qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
g_free(nodename);
- nodename = g_strdup_printf("/uart@%lx",
+ nodename = g_strdup_printf("/soc/ethclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_GEM_CLOCK_FREQ);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3);
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3);
+ ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/ethernet@%lx",
+ (long)memmap[SIFIVE_U_GEM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_GEM].base,
+ 0x0, memmap[SIFIVE_U_GEM].size);
+ qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+ qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ ethclk_phandle, ethclk_phandle, ethclk_phandle);
+ qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
+ sizeof(ethclk_names));
+ qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
+ qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
+ (long)memmap[SIFIVE_U_GEM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/uart@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_UART0].base,
0x0, memmap[SIFIVE_U_UART0].size);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_CLOCK_FREQ / 2);
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
g_free(nodename);
}
const struct MemmapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = g_new0(SiFiveUState, 1);
- MemoryRegion *sys_memory = get_system_memory();
+ MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
+ int i;
- /* Initialize SOC */
- object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
- &error_abort);
- object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
+ /* Initialize SoC */
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ sizeof(s->soc), TYPE_RISCV_U_SOC,
+ &error_abort, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
machine->ram_size, &error_fatal);
- memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base,
- main_mem);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+ main_mem);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
- /* boot rom */
- memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom",
- memmap[SIFIVE_U_MROM].base, &error_fatal);
- memory_region_set_readonly(boot_rom, true);
- memory_region_add_subregion(sys_memory, 0x0, boot_rom);
-
if (machine->kernel_filename) {
load_kernel(machine->kernel_filename);
}
/* dtb: */
};
- /* copy in the reset vector */
- copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_vec));
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+ memmap[SIFIVE_U_MROM].base, &address_space_memory);
/* copy in the device tree */
- qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
- cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base +
- sizeof(reset_vec), s->fdt, s->fdt_size);
+ if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
+ memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
+ error_report("not enough space to store device-tree");
+ exit(1);
+ }
+ qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
+ rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
+ memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
+ &address_space_memory);
+}
+
+static void riscv_sifive_u_soc_init(Object *obj)
+{
+ SiFiveUSoCState *s = RISCV_U_SOC(obj);
+
+ object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
+ TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
+ &error_abort);
+ object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+ &error_abort);
+
+ sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
+ TYPE_CADENCE_GEM);
+}
+
+static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
+{
+ SiFiveUSoCState *s = RISCV_U_SOC(dev);
+ const struct MemmapEntry *memmap = sifive_u_memmap;
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
+ int i;
+ Error *err = NULL;
+ NICInfo *nd = &nd_table[0];
+
+ object_property_set_bool(OBJECT(&s->cpus), true, "realized",
+ &error_abort);
+
+ /* boot rom */
+ memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
+ memmap[SIFIVE_U_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+ mask_rom);
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_U_PLIC].size);
- sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base,
- serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
- /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base,
- serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+ serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+ serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
memmap[SIFIVE_U_CLINT].size, smp_cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
-}
-static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
-{
- return 0;
+ for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
+ plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
+ }
+
+ if (nd->used) {
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+ qdev_set_nic_properties(DEVICE(&s->gem), nd);
+ }
+ object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
+ plic_gpios[SIFIVE_U_GEM_IRQ]);
}
-static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
+static void riscv_sifive_u_machine_init(MachineClass *mc)
{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = riscv_sifive_u_sysbus_device_init;
+ mc->desc = "RISC-V Board compatible with SiFive U SDK";
+ mc->init = riscv_sifive_u_init;
+ mc->max_cpus = 1;
}
-static const TypeInfo riscv_sifive_u_device = {
- .name = TYPE_SIFIVE_U,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SiFiveUState),
- .class_init = riscv_sifive_u_class_init,
-};
+DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
-static void riscv_sifive_u_register_types(void)
+static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
- type_register_static(&riscv_sifive_u_device);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = riscv_sifive_u_soc_realize;
+ /* Reason: Uses serial_hds in realize function, thus can't be used twice */
+ dc->user_creatable = false;
}
-type_init(riscv_sifive_u_register_types);
+static const TypeInfo riscv_sifive_u_soc_type_info = {
+ .name = TYPE_RISCV_U_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(SiFiveUSoCState),
+ .instance_init = riscv_sifive_u_soc_init,
+ .class_init = riscv_sifive_u_soc_class_init,
+};
-static void riscv_sifive_u_machine_init(MachineClass *mc)
+static void riscv_sifive_u_soc_register_types(void)
{
- mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
- mc->max_cpus = 1;
+ type_register_static(&riscv_sifive_u_soc_type_info);
}
-DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
+type_init(riscv_sifive_u_soc_register_types)
projects / qemu.git / blobdiff