target-arm: Fix 11MPCore cache type register value

[qemu.git] / target-arm / cpu-qom.h

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index b6c044a251d1d820b5a3159053c638539806bc63..a61c68d21b555140e9ddd4fef1f757c599d201fd 100644 (file)
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_ARM_CPU_QOM_H
 
 #include "qemu/cpu.h"
-#include "cpu.h"
 
 #define TYPE_ARM_CPU "arm-cpu"
 
@@ -94,6 +93,7 @@ typedef struct ARMCPU {
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
      */
     uint32_t ccsidr[16];
+    uint32_t reset_cbar;
 } ARMCPU;
 
 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)