* Copyright (c) 2006-2007 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
#include "sysbus.h"
-#define GIC_NIRQ 96
-#define NCPU 1
-
-/* Only a single "CPU" interface is present. */
-static inline int
-gic_get_current_cpu(void)
-{
- return 0;
-}
-
-#include "arm_gic.c"
-
typedef struct {
- gic_state gic;
- int iomemtype;
+ SysBusDevice busdev;
+ DeviceState *gic;
+ MemoryRegion container;
} RealViewGICState;
-static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
+static void realview_gic_set_irq(void *opaque, int irq, int level)
{
- gic_state *s = (gic_state *)opaque;
- return gic_cpu_read(s, gic_get_current_cpu(), offset);
+ RealViewGICState *s = (RealViewGICState *)opaque;
+ qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}
-static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+static int realview_gic_init(SysBusDevice *dev)
{
- gic_state *s = (gic_state *)opaque;
- gic_cpu_write(s, gic_get_current_cpu(), offset, value);
-}
+ RealViewGICState *s = FROM_SYSBUS(RealViewGICState, dev);
+ SysBusDevice *busdev;
+ /* The GICs on the RealView boards have a fixed nonconfigurable
+ * number of interrupt lines, so we don't need to expose this as
+ * a qdev property.
+ */
+ int numirq = 96;
-static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
- realview_gic_cpu_read,
- realview_gic_cpu_read,
- realview_gic_cpu_read
-};
+ s->gic = qdev_create(NULL, "arm_gic");
+ qdev_prop_set_uint32(s->gic, "num-cpu", 1);
+ qdev_prop_set_uint32(s->gic, "num-irq", numirq);
+ qdev_init_nofail(s->gic);
+ busdev = sysbus_from_qdev(s->gic);
-static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
- realview_gic_cpu_write,
- realview_gic_cpu_write,
- realview_gic_cpu_write
-};
+ /* Pass through outbound IRQ lines from the GIC */
+ sysbus_pass_irq(dev, busdev);
-static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
-{
- RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ /* Pass through inbound GPIO lines to the GIC */
+ qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32);
+
+ memory_region_init(&s->container, "realview-gic-container", 0x2000);
+ memory_region_add_subregion(&s->container, 0,
+ sysbus_mmio_get_region(busdev, 1));
+ memory_region_add_subregion(&s->container, 0x1000,
+ sysbus_mmio_get_region(busdev, 0));
+ sysbus_init_mmio(dev, &s->container);
+ return 0;
}
-static void realview_gic_init(SysBusDevice *dev)
+static void realview_gic_class_init(ObjectClass *klass, void *data)
{
- RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
- gic_init(&s->gic);
- s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
- realview_gic_cpu_writefn, s);
- sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
+ sdc->init = realview_gic_init;
}
-static void realview_gic_register_devices(void)
+static TypeInfo realview_gic_info = {
+ .name = "realview_gic",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RealViewGICState),
+ .class_init = realview_gic_class_init,
+};
+
+static void realview_gic_register_types(void)
{
- sysbus_register_dev("realview_gic", sizeof(RealViewGICState),
- realview_gic_init);
+ type_register_static(&realview_gic_info);
}
-device_init(realview_gic_register_devices)
+type_init(realview_gic_register_types)