Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.

[qemu.git] / target-mips / TODO

diff --git a/target-mips/TODO b/target-mips/TODO
index e162ea5295b3448b6ed38c45e9aa0fd3195c3d10..bb18fa8d85d633af9bec04d8e6d2af14ead7f5ae 100644 (file)
--- a/target-mips/TODO
+++ b/target-mips/TODO
@@ -3,26 +3,56 @@ Unsolved issues/bugs in the mips/mipsel backend
 
 General
 -------
-- TLB fails cornercase at address wrap around
-- [ls][dw][lr] report broken (aligned) BadVAddr
-- Missing per-CPU instruction decoding, currently all implemented
-  instructions are regarded as valid
-- pcnet32 does not work for little endian emulation on big endian host
-  (probably not mips specific, but observable for mips-malta)
+- Unimplemented ASEs:
+  - MIPS16
+  - MDMX
+  - SmartMIPS
+  - DSP r1
+  - DSP r2
+- MT ASE only partially implemented and not functional
+- Shadow register support only partially implemented,
+  lacks set switching on interrupt/exception.
+- 34K ITC not implemented.
+- A general lack of documentation, especially for technical internals.
+  Existing documentation is x86-centric.
+- Reverse endianness bit not implemented
+- The TLB emulation is very inefficient:
+  Qemu's softmmu implements a x86-style MMU, with separate entries
+  for read/write/execute, a TLB index which is just a modulo of the
+  virtual address, and a set of TLBs for each user/kernel/supervisor
+  MMU mode.
+  MIPS has a single entry for read/write/execute and only one MMU mode.
+  But it is fully associative with randomized entry indices, and uses
+  up to 256 ASID tags as additional matching criterion (which roughly
+  equates to 256 MMU modes). It also has a global flag which causes
+  entries to match regardless of ASID.
+  To cope with these differences, Qemu currently flushes the TLB at
+  each ASID change. Using the MMU modes to implement ASIDs hinges on
+  implementing the global bit efficiently.
+- save/restore of the CPU state is not implemented (see machine.c).
+- Improve cpu state handling:
+  Step 1) Collect all the TC state in a single struct, so we need only
+          a single global pointer for the active TC.
+  Step 2) Use only a single TC context as working context, and copy the
+          contexts on TC switch. Likewise for FPU contexts.
 
 MIPS64
 ------
-- No 64bit TLB support
-- no 64bit wide registers for FPU
-- 64bit mul/div handling broken
-- DM[FT]C not implemented
+- Userland emulation (both n32 and n64) not functional.
 
 "Generic" 4Kc system emulation
 ------------------------------
-- Doesn't correspond to any real hardware.
+- Doesn't correspond to any real hardware. Should be removed some day,
+  U-Boot is the last remaining user.
+
+PICA 61 system emulation
+------------------------
+- No framebuffer support yet.
 
 MALTA system emulation
 ----------------------
 - We fake firmware support instead of doing the real thing
-- 2.4 Kernels receive spurious PIIX4 interrupts, indicates some
-  divergence from actual hardware.
+- Real firmware (YAMON) falls over when trying to init RAM, presumably
+  due to lacking system controller emulation.
+- Bonito system controller not implemented
+- MSC1 system controller not implemented