include/qemu/osdep.h: Don't include qapi/error.h

[qemu.git] / target-ppc / mmu-hash32.c

diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index d4d91dd6e26127e6bb4ae157ed5f45b46c933874..39abb2fd39c49675a3635b836eb35a055c83d557 100644 (file)
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -18,25 +18,18 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 

+#include "qemu/osdep.h"

 #include "cpu.h"
 #include "cpu.h"

-#include "helper.h"
+#include "exec/helper-proto.h"

 #include "sysemu/kvm.h"
 #include "kvm_ppc.h"
 #include "mmu-hash32.h"
 #include "sysemu/kvm.h"
 #include "kvm_ppc.h"
 #include "mmu-hash32.h"

+#include "exec/log.h"

 
 

-//#define DEBUG_MMU

 //#define DEBUG_BAT
 
 //#define DEBUG_BAT
 

-#ifdef DEBUG_MMU
-#  define LOG_MMU(...) qemu_log(__VA_ARGS__)
-#  define LOG_MMU_STATE(env) log_cpu_state((env), 0)
-#else
-#  define LOG_MMU(...) do { } while (0)
-#  define LOG_MMU_STATE(...) do { } while (0)
-#endif
-

 #ifdef DEBUG_BATS
 #ifdef DEBUG_BATS

-#  define LOG_BATS(...) qemu_log(__VA_ARGS__)
+#  define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)

 #else
 #  define LOG_BATS(...) do { } while (0)
 #endif
 #else
 #  define LOG_BATS(...) do { } while (0)
 #endif


@@ -45,77 +38,70 @@ struct mmu_ctx_hash32 {
     hwaddr raddr;      /* Real address              */
     int prot;                      /* Protection bits           */
     int key;                       /* Access key                */
     hwaddr raddr;      /* Real address              */
     int prot;                      /* Protection bits           */
     int key;                       /* Access key                */

-    int nx;                        /* Non-execute area          */

 };
 
 };
 

-static int ppc_hash32_pp_check(int key, int pp, int nx)
+static int ppc_hash32_pp_prot(int key, int pp, int nx)

 {
 {

-    int access;
+    int prot;

 
 

-    /* Compute access rights */
-    access = 0;

     if (key == 0) {
         switch (pp) {
         case 0x0:
         case 0x1:
         case 0x2:
     if (key == 0) {
         switch (pp) {
         case 0x0:
         case 0x1:
         case 0x2:

-            access |= PAGE_WRITE;
-            /* No break here */
+            prot = PAGE_READ | PAGE_WRITE;
+            break;
+

         case 0x3:
         case 0x3:

-            access |= PAGE_READ;
+            prot = PAGE_READ;

             break;
             break;

+
+        default:
+            abort();

         }
     } else {
         switch (pp) {
         case 0x0:
         }
     } else {
         switch (pp) {
         case 0x0:

-            access = 0;
+            prot = 0;

             break;
             break;

+

         case 0x1:
         case 0x3:
         case 0x1:
         case 0x3:

-            access = PAGE_READ;
+            prot = PAGE_READ;

             break;
             break;

+

         case 0x2:
         case 0x2:

-            access = PAGE_READ | PAGE_WRITE;
+            prot = PAGE_READ | PAGE_WRITE;

             break;
             break;

+
+        default:
+            abort();

         }
     }
     if (nx == 0) {
         }
     }
     if (nx == 0) {

-        access |= PAGE_EXEC;
+        prot |= PAGE_EXEC;

     }
 
     }
 

-    return access;
+    return prot;

 }
 
 }
 

-static int ppc_hash32_check_prot(int prot, int rwx)
+static int ppc_hash32_pte_prot(PowerPCCPU *cpu,
+                               target_ulong sr, ppc_hash_pte32_t pte)

 {
 {

-    int ret;
+    CPUPPCState *env = &cpu->env;
+    unsigned pp, key;

 
 

-    if (rwx == 2) {
-        if (prot & PAGE_EXEC) {
-            ret = 0;
-        } else {
-            ret = -2;
-        }
-    } else if (rwx) {
-        if (prot & PAGE_WRITE) {
-            ret = 0;
-        } else {
-            ret = -2;
-        }
-    } else {
-        if (prot & PAGE_READ) {
-            ret = 0;
-        } else {
-            ret = -2;
-        }
-    }
+    key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
+    pp = pte.pte1 & HPTE32_R_PP;

 
 

-    return ret;
+    return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));

 }
 
 }
 

-static target_ulong hash32_bat_size(CPUPPCState *env,
+static target_ulong hash32_bat_size(PowerPCCPU *cpu,

                                     target_ulong batu, target_ulong batl)
 {
                                     target_ulong batu, target_ulong batl)
 {

+    CPUPPCState *env = &cpu->env;
+

     if ((msr_pr && !(batu & BATU32_VP))
         || (!msr_pr && !(batu & BATU32_VS))) {
         return 0;
     if ((msr_pr && !(batu & BATU32_VP))
         || (!msr_pr && !(batu & BATU32_VS))) {
         return 0;


@@ -124,7 +110,7 @@ static target_ulong hash32_bat_size(CPUPPCState *env,
     return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
 }
 
     return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
 }
 

-static int hash32_bat_prot(CPUPPCState *env,
+static int hash32_bat_prot(PowerPCCPU *cpu,

                            target_ulong batu, target_ulong batl)
 {
     int pp, prot;
                            target_ulong batu, target_ulong batl)
 {
     int pp, prot;


@@ -140,7 +126,7 @@ static int hash32_bat_prot(CPUPPCState *env,
     return prot;
 }
 
     return prot;
 }
 

-static target_ulong hash32_bat_601_size(CPUPPCState *env,
+static target_ulong hash32_bat_601_size(PowerPCCPU *cpu,

                                 target_ulong batu, target_ulong batl)
 {
     if (!(batl & BATL32_601_V)) {
                                 target_ulong batu, target_ulong batl)
 {
     if (!(batl & BATL32_601_V)) {


@@ -150,9 +136,10 @@ static target_ulong hash32_bat_601_size(CPUPPCState *env,
     return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
 }
 
     return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
 }
 

-static int hash32_bat_601_prot(CPUPPCState *env,
+static int hash32_bat_601_prot(PowerPCCPU *cpu,

                                target_ulong batu, target_ulong batl)
 {
                                target_ulong batu, target_ulong batl)
 {

+    CPUPPCState *env = &cpu->env;

     int key, pp;
 
     pp = batu & BATU32_601_PP;
     int key, pp;
 
     pp = batu & BATU32_601_PP;


@@ -161,12 +148,13 @@ static int hash32_bat_601_prot(CPUPPCState *env,
     } else {
         key = !!(batu & BATU32_601_KP);
     }
     } else {
         key = !!(batu & BATU32_601_KP);
     }

-    return ppc_hash32_pp_check(key, pp, 0);
+    return ppc_hash32_pp_prot(key, pp, 0);

 }
 
 }
 

-static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
+static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx,

                                     int *prot)
 {
                                     int *prot)
 {

+    CPUPPCState *env = &cpu->env;

     target_ulong *BATlt, *BATut;
     int i;
 
     target_ulong *BATlt, *BATut;
     int i;
 


@@ -185,9 +173,9 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
         target_ulong mask;
 
         if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
         target_ulong mask;
 
         if (unlikely(env->mmu_model == POWERPC_MMU_601)) {

-            mask = hash32_bat_601_size(env, batu, batl);
+            mask = hash32_bat_601_size(cpu, batu, batl);

         } else {
         } else {

-            mask = hash32_bat_size(env, batu, batl);
+            mask = hash32_bat_size(cpu, batu, batl);

         }
         LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                  " BATl " TARGET_FMT_lx "\n", __func__,
         }
         LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                  " BATl " TARGET_FMT_lx "\n", __func__,


@@ -197,9 +185,9 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
             hwaddr raddr = (batl & mask) | (ea & ~mask);
 
             if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
             hwaddr raddr = (batl & mask) | (ea & ~mask);
 
             if (unlikely(env->mmu_model == POWERPC_MMU_601)) {

-                *prot = hash32_bat_601_prot(env, batu, batl);
+                *prot = hash32_bat_601_prot(cpu, batu, batl);

             } else {
             } else {

-                *prot = hash32_bat_prot(env, batu, batl);
+                *prot = hash32_bat_prot(cpu, batu, batl);

             }
 
             return raddr & TARGET_PAGE_MASK;
             }
 
             return raddr & TARGET_PAGE_MASK;


@@ -228,13 +216,15 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
     return -1;
 }
 
     return -1;
 }
 

-static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
+static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,

                                    target_ulong eaddr, int rwx,
                                    hwaddr *raddr, int *prot)
 {
                                    target_ulong eaddr, int rwx,
                                    hwaddr *raddr, int *prot)
 {

+    CPUState *cs = CPU(cpu);
+    CPUPPCState *env = &cpu->env;

     int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
 
     int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
 

-    LOG_MMU("direct store...\n");
+    qemu_log_mask(CPU_LOG_MMU, "direct store...\n");

 
     if ((sr & 0x1FF00000) >> 20 == 0x07f) {
         /* Memory-forced I/O controller interface access */
 
     if ((sr & 0x1FF00000) >> 20 == 0x07f) {
         /* Memory-forced I/O controller interface access */


@@ -248,7 +238,9 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
 
     if (rwx == 2) {
         /* No code fetch is allowed in direct-store areas */
 
     if (rwx == 2) {
         /* No code fetch is allowed in direct-store areas */

-        return -4;
+        cs->exception_index = POWERPC_EXCP_ISI;
+        env->error_code = 0x10000000;
+        return 1;

     }
 
     switch (env->access_type) {
     }
 
     switch (env->access_type) {


@@ -257,10 +249,20 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
         break;
     case ACCESS_FLOAT:
         /* Floating point load/store */
         break;
     case ACCESS_FLOAT:
         /* Floating point load/store */

-        return -4;
+        cs->exception_index = POWERPC_EXCP_ALIGN;
+        env->error_code = POWERPC_EXCP_ALIGN_FP;
+        env->spr[SPR_DAR] = eaddr;
+        return 1;

     case ACCESS_RES:
         /* lwarx, ldarx or srwcx. */
     case ACCESS_RES:
         /* lwarx, ldarx or srwcx. */

-        return -4;
+        env->error_code = 0;
+        env->spr[SPR_DAR] = eaddr;
+        if (rwx == 1) {
+            env->spr[SPR_DSISR] = 0x06000000;
+        } else {
+            env->spr[SPR_DSISR] = 0x04000000;
+        }
+        return 1;

     case ACCESS_CACHE:
         /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
         /* Should make the instruction do no-op.
     case ACCESS_CACHE:
         /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
         /* Should make the instruction do no-op.


@@ -270,51 +272,43 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
         return 0;
     case ACCESS_EXT:
         /* eciwx or ecowx */
         return 0;
     case ACCESS_EXT:
         /* eciwx or ecowx */

-        return -4;
+        cs->exception_index = POWERPC_EXCP_DSI;
+        env->error_code = 0;
+        env->spr[SPR_DAR] = eaddr;
+        if (rwx == 1) {
+            env->spr[SPR_DSISR] = 0x06100000;
+        } else {
+            env->spr[SPR_DSISR] = 0x04100000;
+        }
+        return 1;

     default:
     default:

-        qemu_log("ERROR: instruction should not need "
+        cpu_abort(cs, "ERROR: instruction should not need "

                  "address translation\n");
                  "address translation\n");

-        return -4;

     }
     if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
         *raddr = eaddr;
     }
     if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
         *raddr = eaddr;

-        return 2;
+        return 0;

     } else {
     } else {

-        return -2;
-    }
-}
-
-static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, uint32_t *pte1p,
-                                       int ret, int rwx)
-{
-    int store = 0;
-
-    /* Update page flags */
-    if (!(*pte1p & HPTE32_R_R)) {
-        /* Update accessed flag */
-        *pte1p |= HPTE32_R_R;
-        store = 1;
-    }
-    if (!(*pte1p & HPTE32_R_C)) {
-        if (rwx == 1 && ret == 0) {
-            /* Update changed flag */
-            *pte1p |= HPTE32_R_C;
-            store = 1;
+        cs->exception_index = POWERPC_EXCP_DSI;
+        env->error_code = 0;
+        env->spr[SPR_DAR] = eaddr;
+        if (rwx == 1) {
+            env->spr[SPR_DSISR] = 0x0a000000;

         } else {
         } else {

-            /* Force page fault for first write access */
-            ctx->prot &= ~PAGE_WRITE;
+            env->spr[SPR_DSISR] = 0x08000000;

         }
         }

+        return 1;

     }
     }

-
-    return store;

 }
 
 }
 

-hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
+hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)

 {
 {

+    CPUPPCState *env = &cpu->env;
+

     return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
 }
 
     return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
 }
 

-static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
+static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,

                                      bool secondary, target_ulong ptem,
                                      ppc_hash_pte32_t *pte)
 {
                                      bool secondary, target_ulong ptem,
                                      ppc_hash_pte32_t *pte)
 {


@@ -323,8 +317,8 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
     int i;
 
     for (i = 0; i < HPTES_PER_GROUP; i++) {
     int i;
 
     for (i = 0; i < HPTES_PER_GROUP; i++) {

-        pte0 = ppc_hash32_load_hpte0(env, pte_offset);
-        pte1 = ppc_hash32_load_hpte1(env, pte_offset);
+        pte0 = ppc_hash32_load_hpte0(cpu, pte_offset);
+        pte1 = ppc_hash32_load_hpte1(cpu, pte_offset);

 
         if ((pte0 & HPTE32_V_VALID)
             && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
 
         if ((pte0 & HPTE32_V_VALID)
             && (secondary == !!(pte0 & HPTE32_V_SECONDARY))


@@ -340,10 +334,11 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
     return -1;
 }
 
     return -1;
 }
 

-static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
+static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,

                                      target_ulong sr, target_ulong eaddr,
                                      ppc_hash_pte32_t *pte)
 {
                                      target_ulong sr, target_ulong eaddr,
                                      ppc_hash_pte32_t *pte)
 {

+    CPUPPCState *env = &cpu->env;

     hwaddr pteg_off, pte_offset;
     hwaddr hash;
     uint32_t vsid, pgidx, ptem;
     hwaddr pteg_off, pte_offset;
     hwaddr hash;
     uint32_t vsid, pgidx, ptem;


@@ -354,56 +349,90 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
     ptem = (vsid << 7) | (pgidx >> 10);
 
     /* Page address translation */
     ptem = (vsid << 7) | (pgidx >> 10);
 
     /* Page address translation */

-    LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
+    qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
+            " htab_mask " TARGET_FMT_plx

             " hash " TARGET_FMT_plx "\n",
             env->htab_base, env->htab_mask, hash);
 
     /* Primary PTEG lookup */
             " hash " TARGET_FMT_plx "\n",
             env->htab_base, env->htab_mask, hash);
 
     /* Primary PTEG lookup */

-    LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+    qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx

             " vsid=%" PRIx32 " ptem=%" PRIx32
             " hash=" TARGET_FMT_plx "\n",
             env->htab_base, env->htab_mask, vsid, ptem, hash);
             " vsid=%" PRIx32 " ptem=%" PRIx32
             " hash=" TARGET_FMT_plx "\n",
             env->htab_base, env->htab_mask, vsid, ptem, hash);

-    pteg_off = get_pteg_offset32(env, hash);
-    pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
+    pteg_off = get_pteg_offset32(cpu, hash);
+    pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);

     if (pte_offset == -1) {
         /* Secondary PTEG lookup */
     if (pte_offset == -1) {
         /* Secondary PTEG lookup */

-        LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+        qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx

                 " vsid=%" PRIx32 " api=%" PRIx32
                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
                 env->htab_mask, vsid, ptem, ~hash);
                 " vsid=%" PRIx32 " api=%" PRIx32
                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
                 env->htab_mask, vsid, ptem, ~hash);

-        pteg_off = get_pteg_offset32(env, ~hash);
-        pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
+        pteg_off = get_pteg_offset32(cpu, ~hash);
+        pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);

     }
 
     return pte_offset;
 }
 
     }
 
     return pte_offset;
 }
 

-static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
-                                target_ulong eaddr, int rwx)
+static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
+                                   target_ulong eaddr)

 {
 {

-    int ret;
+    hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
+    hwaddr mask = ~TARGET_PAGE_MASK;
+
+    return (rpn & ~mask) | (eaddr & mask);
+}
+
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
+                                int mmu_idx)
+{
+    CPUState *cs = CPU(cpu);
+    CPUPPCState *env = &cpu->env;

     target_ulong sr;
     hwaddr pte_offset;
     ppc_hash_pte32_t pte;
     target_ulong sr;
     hwaddr pte_offset;
     ppc_hash_pte32_t pte;

+    int prot;
+    uint32_t new_pte1;
+    const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
+    hwaddr raddr;

 
     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 
     /* 1. Handle real mode accesses */
     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
         /* Translation is off */
 
     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 
     /* 1. Handle real mode accesses */
     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
         /* Translation is off */

-        ctx->raddr = eaddr;
-        ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
+        raddr = eaddr;
+        tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
+                     TARGET_PAGE_SIZE);

         return 0;
     }
 
     /* 2. Check Block Address Translation entries (BATs) */
     if (env->nb_BATs != 0) {
         return 0;
     }
 
     /* 2. Check Block Address Translation entries (BATs) */
     if (env->nb_BATs != 0) {

-        ctx->raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &ctx->prot);
-        if (ctx->raddr != -1) {
-            ret = ppc_hash32_check_prot(ctx->prot, rwx);
-            if (ret == 0) {
-                return 0;
+        raddr = ppc_hash32_bat_lookup(cpu, eaddr, rwx, &prot);
+        if (raddr != -1) {
+            if (need_prot[rwx] & ~prot) {
+                if (rwx == 2) {
+                    cs->exception_index = POWERPC_EXCP_ISI;
+                    env->error_code = 0x08000000;
+                } else {
+                    cs->exception_index = POWERPC_EXCP_DSI;
+                    env->error_code = 0;
+                    env->spr[SPR_DAR] = eaddr;
+                    if (rwx == 1) {
+                        env->spr[SPR_DSISR] = 0x0a000000;
+                    } else {
+                        env->spr[SPR_DSISR] = 0x08000000;
+                    }
+                }
+                return 1;

             }
             }

+
+            tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
+                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
+                         TARGET_PAGE_SIZE);
+            return 0;

         }
     }
 
         }
     }
 


@@ -412,176 +441,127 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
 
     /* 4. Handle direct store segments */
     if (sr & SR32_T) {
 
     /* 4. Handle direct store segments */
     if (sr & SR32_T) {

-        return ppc_hash32_direct_store(env, sr, eaddr, rwx,
-                                       &ctx->raddr, &ctx->prot);
+        if (ppc_hash32_direct_store(cpu, sr, eaddr, rwx,
+                                    &raddr, &prot) == 0) {
+            tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
+                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
+                         TARGET_PAGE_SIZE);
+            return 0;
+        } else {
+            return 1;
+        }

     }
 
     /* 5. Check for segment level no-execute violation */
     }
 
     /* 5. Check for segment level no-execute violation */

-    ctx->nx = !!(sr & SR32_NX);
-    if ((rwx == 2) && ctx->nx) {
-        return -3;
+    if ((rwx == 2) && (sr & SR32_NX)) {
+        cs->exception_index = POWERPC_EXCP_ISI;
+        env->error_code = 0x10000000;
+        return 1;

     }
 
     /* 6. Locate the PTE in the hash table */
     }
 
     /* 6. Locate the PTE in the hash table */

-    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
+    pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);

     if (pte_offset == -1) {
     if (pte_offset == -1) {

-        return -1;
+        if (rwx == 2) {
+            cs->exception_index = POWERPC_EXCP_ISI;
+            env->error_code = 0x40000000;
+        } else {
+            cs->exception_index = POWERPC_EXCP_DSI;
+            env->error_code = 0;
+            env->spr[SPR_DAR] = eaddr;
+            if (rwx == 1) {
+                env->spr[SPR_DSISR] = 0x42000000;
+            } else {
+                env->spr[SPR_DSISR] = 0x40000000;
+            }
+        }
+
+        return 1;

     }
     }

-    LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
+    qemu_log_mask(CPU_LOG_MMU,
+                "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);

 
     /* 7. Check access permissions */
 
     /* 7. Check access permissions */

-    ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) ||
-                ((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0;

 
 

-    int access, pp;
+    prot = ppc_hash32_pte_prot(cpu, sr, pte);

 
 

-    pp = pte.pte1 & HPTE32_R_PP;
-    /* Compute access rights */
-    access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx);
-    /* Keep the matching PTE informations */
-    ctx->raddr = pte.pte1;
-    ctx->prot = access;
-    ret = ppc_hash32_check_prot(ctx->prot, rwx);
-    if (ret == 0) {
-        /* Access granted */
-        LOG_MMU("PTE access granted !\n");
-    } else {
+    if (need_prot[rwx] & ~prot) {

         /* Access right violation */
         /* Access right violation */

-        LOG_MMU("PTE access rejected\n");
+        qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
+        if (rwx == 2) {
+            cs->exception_index = POWERPC_EXCP_ISI;
+            env->error_code = 0x08000000;
+        } else {
+            cs->exception_index = POWERPC_EXCP_DSI;
+            env->error_code = 0;
+            env->spr[SPR_DAR] = eaddr;
+            if (rwx == 1) {
+                env->spr[SPR_DSISR] = 0x0a000000;
+            } else {
+                env->spr[SPR_DSISR] = 0x08000000;
+            }
+        }
+        return 1;

     }
 
     }
 

-    /* Update page flags */
-    if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
-        ppc_hash32_store_hpte1(env, pte_offset, pte.pte1);
-    }
+    qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");

 
 

-    return ret;
-}
+    /* 8. Update PTE referenced and changed bits if necessary */

 
 

-hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
-{
-    struct mmu_ctx_hash32 ctx;
+    new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
+    if (rwx == 1) {
+        new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
+    } else {
+        /* Treat the page as read-only for now, so that a later write
+         * will pass through this function again to set the C bit */
+        prot &= ~PAGE_WRITE;
+    }

 
 

-    /* FIXME: Will not behave sanely for direct store segments, but
-     * they're almost never used */
-    if (unlikely(ppc_hash32_translate(env, &ctx, addr, 0)
-                 != 0)) {
-        return -1;
+    if (new_pte1 != pte.pte1) {
+        ppc_hash32_store_hpte1(cpu, pte_offset, new_pte1);

     }
 
     }
 

-    return ctx.raddr & TARGET_PAGE_MASK;
+    /* 9. Determine the real address from the PTE */
+
+    raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
+
+    tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+                 prot, mmu_idx, TARGET_PAGE_SIZE);
+
+    return 0;

 }
 
 }
 

-int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
-                                int mmu_idx)
+hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)

 {
 {

-    struct mmu_ctx_hash32 ctx;
-    int ret = 0;
-
-    ret = ppc_hash32_translate(env, &ctx, address, rwx);
-    if (ret == 0) {
-        tlb_set_page(env, address & TARGET_PAGE_MASK,
-                     ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
-                     mmu_idx, TARGET_PAGE_SIZE);
-        ret = 0;
-    } else if (ret < 0) {
-        LOG_MMU_STATE(env);
-        if (rwx == 2) {
-            switch (ret) {
-            case -1:
-                /* No matches in page tables or TLB */
-                env->exception_index = POWERPC_EXCP_ISI;
-                env->error_code = 0x40000000;
-                break;
-            case -2:
-                /* Access rights violation */
-                env->exception_index = POWERPC_EXCP_ISI;
-                env->error_code = 0x08000000;
-                break;
-            case -3:
-                /* No execute protection violation */
-                env->exception_index = POWERPC_EXCP_ISI;
-                env->error_code = 0x10000000;
-                break;
-            case -4:
-                /* Direct store exception */
-                /* No code fetch is allowed in direct-store areas */
-                env->exception_index = POWERPC_EXCP_ISI;
-                env->error_code = 0x10000000;
-                break;
-            }
-        } else {
-            switch (ret) {
-            case -1:
-                /* No matches in page tables or TLB */
-                env->exception_index = POWERPC_EXCP_DSI;
-                env->error_code = 0;
-                env->spr[SPR_DAR] = address;
-                if (rwx == 1) {
-                    env->spr[SPR_DSISR] = 0x42000000;
-                } else {
-                    env->spr[SPR_DSISR] = 0x40000000;
-                }
-                break;
-            case -2:
-                /* Access rights violation */
-                env->exception_index = POWERPC_EXCP_DSI;
-                env->error_code = 0;
-                env->spr[SPR_DAR] = address;
-                if (rwx == 1) {
-                    env->spr[SPR_DSISR] = 0x0A000000;
-                } else {
-                    env->spr[SPR_DSISR] = 0x08000000;
-                }
-                break;
-            case -4:
-                /* Direct store exception */
-                switch (env->access_type) {
-                case ACCESS_FLOAT:
-                    /* Floating point load/store */
-                    env->exception_index = POWERPC_EXCP_ALIGN;
-                    env->error_code = POWERPC_EXCP_ALIGN_FP;
-                    env->spr[SPR_DAR] = address;
-                    break;
-                case ACCESS_RES:
-                    /* lwarx, ldarx or stwcx. */
-                    env->exception_index = POWERPC_EXCP_DSI;
-                    env->error_code = 0;
-                    env->spr[SPR_DAR] = address;
-                    if (rwx == 1) {
-                        env->spr[SPR_DSISR] = 0x06000000;
-                    } else {
-                        env->spr[SPR_DSISR] = 0x04000000;
-                    }
-                    break;
-                case ACCESS_EXT:
-                    /* eciwx or ecowx */
-                    env->exception_index = POWERPC_EXCP_DSI;
-                    env->error_code = 0;
-                    env->spr[SPR_DAR] = address;
-                    if (rwx == 1) {
-                        env->spr[SPR_DSISR] = 0x06100000;
-                    } else {
-                        env->spr[SPR_DSISR] = 0x04100000;
-                    }
-                    break;
-                default:
-                    printf("DSI: invalid exception (%d)\n", ret);
-                    env->exception_index = POWERPC_EXCP_PROGRAM;
-                    env->error_code =
-                        POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
-                    env->spr[SPR_DAR] = address;
-                    break;
-                }
-                break;
-            }
+    CPUPPCState *env = &cpu->env;
+    target_ulong sr;
+    hwaddr pte_offset;
+    ppc_hash_pte32_t pte;
+    int prot;
+
+    if (msr_dr == 0) {
+        /* Translation is off */
+        return eaddr;
+    }
+
+    if (env->nb_BATs != 0) {
+        hwaddr raddr = ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot);
+        if (raddr != -1) {
+            return raddr;

         }
         }

-#if 0
-        printf("%s: set exception to %d %02x\n", __func__,
-               env->exception, env->error_code);
-#endif
-        ret = 1;

     }
 
     }
 

-    return ret;
+    sr = env->sr[eaddr >> 28];
+
+    if (sr & SR32_T) {
+        /* FIXME: Add suitable debug support for Direct Store segments */
+        return -1;
+    }
+
+    pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
+    if (pte_offset == -1) {
+        return -1;
+    }
+
+    return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;

 }
 }