*/
#include "sysbus.h"
-#include "qemu-char.h"
-#include "qemu-timer.h"
-#include "qemu-log.h"
+#include "qemu/timer.h"
+#include "ptimer.h"
+#include "qemu/log.h"
#include "qdev-addr.h"
-#include "xilinx_axidma.h"
+#include "stream.h"
#define D(x)
SDESC_STATUS_COMPLETE = (1 << 31)
};
-struct AXIStream {
+struct Stream {
QEMUBH *bh;
ptimer_state *ptimer;
qemu_irq irq;
struct XilinxAXIDMA {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t freqhz;
- void *dmach;
+ StreamSlave *tx_dev;
- struct AXIStream streams[2];
+ struct Stream streams[2];
};
/*
return d->control & SDESC_CTRL_EOF;
}
-static inline int stream_resetting(struct AXIStream *s)
+static inline int stream_resetting(struct Stream *s)
{
return !!(s->regs[R_DMACR] & DMACR_RESET);
}
-static inline int stream_running(struct AXIStream *s)
+static inline int stream_running(struct Stream *s)
{
return s->regs[R_DMACR] & DMACR_RUNSTOP;
}
-static inline int stream_halted(struct AXIStream *s)
+static inline int stream_halted(struct Stream *s)
{
return s->regs[R_DMASR] & DMASR_HALTED;
}
-static inline int stream_idle(struct AXIStream *s)
+static inline int stream_idle(struct Stream *s)
{
return !!(s->regs[R_DMASR] & DMASR_IDLE);
}
-static void stream_reset(struct AXIStream *s)
+static void stream_reset(struct Stream *s)
{
s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
}
/* Map an offset addr into a channel index. */
-static inline int streamid_from_addr(target_phys_addr_t addr)
+static inline int streamid_from_addr(hwaddr addr)
{
int sid;
}
#endif
-static void stream_desc_load(struct AXIStream *s, target_phys_addr_t addr)
+static void stream_desc_load(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
int i;
}
}
-static void stream_desc_store(struct AXIStream *s, target_phys_addr_t addr)
+static void stream_desc_store(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
int i;
cpu_physical_memory_write(addr, (void *) d, sizeof *d);
}
-static void stream_update_irq(struct AXIStream *s)
+static void stream_update_irq(struct Stream *s)
{
unsigned int pending, mask, irq;
qemu_set_irq(s->irq, !!irq);
}
-static void stream_reload_complete_cnt(struct AXIStream *s)
+static void stream_reload_complete_cnt(struct Stream *s)
{
unsigned int comp_th;
comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
static void timer_hit(void *opaque)
{
- struct AXIStream *s = opaque;
+ struct Stream *s = opaque;
stream_reload_complete_cnt(s);
s->regs[R_DMASR] |= DMASR_DLY_IRQ;
stream_update_irq(s);
}
-static void stream_complete(struct AXIStream *s)
+static void stream_complete(struct Stream *s)
{
unsigned int comp_delay;
}
}
-static void stream_process_mem2s(struct AXIStream *s,
- struct XilinxDMAConnection *dmach)
+static void stream_process_mem2s(struct Stream *s,
+ StreamSlave *tx_dev)
{
uint32_t prev_d;
unsigned char txbuf[16 * 1024];
s->pos += txlen;
if (stream_desc_eof(&s->desc)) {
- xlx_dma_push_to_client(dmach, txbuf, s->pos, app);
+ stream_push(tx_dev, txbuf, s->pos, app);
s->pos = 0;
stream_complete(s);
}
}
}
-static void stream_process_s2mem(struct AXIStream *s,
+static void stream_process_s2mem(struct Stream *s,
unsigned char *buf, size_t len, uint32_t *app)
{
uint32_t prev_d;
}
}
-static
-void axidma_push(void *opaque, unsigned char *buf, size_t len, uint32_t *app)
+static void
+axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
{
- struct XilinxAXIDMA *d = opaque;
- struct AXIStream *s = &d->streams[1];
+ struct XilinxAXIDMA *d = FROM_SYSBUS(typeof(*d), SYS_BUS_DEVICE(obj));
+ struct Stream *s = &d->streams[1];
if (!app) {
hw_error("No stream app data!\n");
stream_update_irq(s);
}
-static uint32_t axidma_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t axidma_read(void *opaque, hwaddr addr,
+ unsigned size)
{
struct XilinxAXIDMA *d = opaque;
- struct AXIStream *s;
+ struct Stream *s;
uint32_t r = 0;
int sid;
}
-static void
-axidma_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void axidma_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct XilinxAXIDMA *d = opaque;
- struct AXIStream *s;
+ struct Stream *s;
int sid;
sid = streamid_from_addr(addr);
s->regs[addr] = value;
s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
if (!sid) {
- stream_process_mem2s(s, d->dmach);
+ stream_process_mem2s(s, d->tx_dev);
}
break;
default:
stream_update_irq(s);
}
-static CPUReadMemoryFunc * const axidma_read[] = {
- &axidma_readl,
- &axidma_readl,
- &axidma_readl,
-};
-
-static CPUWriteMemoryFunc * const axidma_write[] = {
- &axidma_writel,
- &axidma_writel,
- &axidma_writel,
+static const MemoryRegionOps axidma_ops = {
+ .read = axidma_read,
+ .write = axidma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int xilinx_axidma_init(SysBusDevice *dev)
{
struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev);
- int axidma_regs;
int i;
- sysbus_init_irq(dev, &s->streams[1].irq);
sysbus_init_irq(dev, &s->streams[0].irq);
+ sysbus_init_irq(dev, &s->streams[1].irq);
- if (!s->dmach) {
- hw_error("Unconnected DMA channel.\n");
- }
-
- xlx_dma_connect_dma(s->dmach, s, axidma_push);
-
- axidma_regs = cpu_register_io_memory(axidma_read, axidma_write, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4 * 2, axidma_regs);
+ memory_region_init_io(&s->iomem, &axidma_ops, s,
+ "xlnx.axi-dma", R_MAX * 4 * 2);
+ sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < 2; i++) {
stream_reset(&s->streams[i]);
return 0;
}
-static SysBusDeviceInfo axidma_info = {
- .init = xilinx_axidma_init,
- .qdev.name = "xilinx,axidma",
- .qdev.size = sizeof(struct XilinxAXIDMA),
- .qdev.props = (Property[]) {
- DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000),
- DEFINE_PROP_PTR("dmach", struct XilinxAXIDMA, dmach),
- DEFINE_PROP_END_OF_LIST(),
+static void xilinx_axidma_initfn(Object *obj)
+{
+ struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
+
+ object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
+ (Object **) &s->tx_dev, NULL);
+}
+
+static Property axidma_properties[] = {
+ DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void axidma_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
+
+ k->init = xilinx_axidma_init;
+ dc->props = axidma_properties;
+ ssc->push = axidma_push;
+}
+
+static const TypeInfo axidma_info = {
+ .name = "xlnx.axi-dma",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct XilinxAXIDMA),
+ .class_init = axidma_class_init,
+ .instance_init = xilinx_axidma_initfn,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_STREAM_SLAVE },
+ { }
}
};
-static void xilinx_axidma_register(void)
+static void xilinx_axidma_register_types(void)
{
- sysbus_register_withprop(&axidma_info);
+ type_register_static(&axidma_info);
}
-device_init(xilinx_axidma_register)
+type_init(xilinx_axidma_register_types)
projects / qemu.git / blobdiff