* S/390 virtual CPU header
*
* Copyright (c) 2009 Ulrich Hecht
+ * Copyright IBM Corp. 2012, 2018
*
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * This library is distributed in the hope that it will be useful,
+ * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
+ * General Public License for more details.
*
- * Contributions after 2012-10-29 are licensed under the terms of the
- * GNU GPL, version 2 or (at your option) any later version.
- *
- * You should have received a copy of the GNU (Lesser) General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef S390X_CPU_H
#define S390X_CPU_H
-#include "qemu-common.h"
#include "cpu-qom.h"
#include "cpu_models.h"
-
-#define TARGET_LONG_BITS 64
-
-#define ELF_MACHINE_UNAME "S390X"
-
-#define CPUArchState struct CPUS390XState
-
#include "exec/cpu-defs.h"
-#define TARGET_PAGE_BITS 12
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define ELF_MACHINE_UNAME "S390X"
-#include "exec/cpu-all.h"
+/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-#define NB_MMU_MODES 4
#define TARGET_INSN_START_EXTRA_WORDS 1
#define MMU_MODE0_SUFFIX _primary
* The floating point registers are part of the vector registers.
* vregs[0][0] -> vregs[15][0] are 16 floating point registers
*/
- CPU_DoubleU vregs[32][2]; /* vector registers */
+ uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
uint32_t aregs[16]; /* access registers */
uint8_t riccb[64]; /* runtime instrumentation control */
uint64_t gscb[4]; /* guarded storage control */
+ uint64_t etoken; /* etoken */
+ uint64_t etoken_extension; /* etoken extension */
/* Fields up to this point are not cleared by initial CPU reset */
struct {} start_initial_reset_fields;
PSW psw;
+ S390CrashReason crash_reason;
+
uint64_t cc_src;
uint64_t cc_dst;
uint64_t cc_vr;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
#if !defined(CONFIG_USER_ONLY)
uint32_t core_id; /* PoP "CPU address", same as cpu_index */
uint64_t cpuid;
#endif
- uint64_t tod_offset;
- uint64_t tod_basetime;
QEMUTimer *tod_timer;
QEMUTimer *cpu_timer;
* architectures, there is a difference between a halt and a stop on s390.
* If all cpus are either stopped (including check stop) or in the disabled
* wait state, the vm can be shut down.
+ * The acceptable cpu_state values are defined in the CpuInfoS390State
+ * enum.
*/
-#define CPU_STATE_UNINITIALIZED 0x00
-#define CPU_STATE_STOPPED 0x01
-#define CPU_STATE_CHECK_STOP 0x02
-#define CPU_STATE_OPERATING 0x03
-#define CPU_STATE_LOAD 0x04
uint8_t cpu_state;
/* currently processed sigp order */
};
-static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
+static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
{
return &cs->vregs[nr][0];
}
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUS390XState env;
S390CPUModel *model;
/* needed for live migration */
uint32_t irqstate_saved_size;
};
-static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
-{
- return container_of(env, S390CPU, env);
-}
-
-#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
-
-#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY
-extern const struct VMStateDescription vmstate_s390_cpu;
+extern const VMStateDescription vmstate_s390_cpu;
#endif
/* distinguish between 24 bit and 31 bit addressing */
#define PGM_SPECIAL_OP 0x0013
#define PGM_OPERAND 0x0015
#define PGM_TRACE_TABLE 0x0016
+#define PGM_VECTOR_PROCESSING 0x001b
#define PGM_SPACE_SWITCH 0x001c
#define PGM_HFP_SQRT 0x001d
#define PGM_PC_TRANS_SPEC 0x001f
/* PSW defines */
#undef PSW_MASK_PER
+#undef PSW_MASK_UNUSED_2
+#undef PSW_MASK_UNUSED_3
#undef PSW_MASK_DAT
#undef PSW_MASK_IO
#undef PSW_MASK_EXT
#undef PSW_MASK_ESA_ADDR
#define PSW_MASK_PER 0x4000000000000000ULL
+#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
+#define PSW_MASK_UNUSED_3 0x1000000000000000ULL
#define PSW_MASK_DAT 0x0400000000000000ULL
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
#define FLAG_MASK_PSW_SHIFT 31
#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
-#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
+#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
| FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
+/* we'll use some unused PSW positions to store CR flags in tb flags */
+#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
+
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
#define CR0_SECONDARY 0x0000000004000000ULL
#define CR0_EDAT 0x0000000000800000ULL
+#define CR0_AFP 0x0000000000040000ULL
+#define CR0_VECTOR 0x0000000000020000ULL
#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
#define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
#define CR0_CKC_SC 0x0000000000000800ULL
static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
{
+ if (!(env->psw.mask & PSW_MASK_DAT)) {
+ return MMU_REAL_IDX;
+ }
+
switch (env->psw.mask & PSW_MASK_ASC) {
case PSW_ASC_PRIMARY:
return MMU_PRIMARY_IDX;
*pc = env->psw.addr;
*cs_base = env->ex_value;
*flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ if (env->cregs[0] & CR0_AFP) {
+ *flags |= FLAG_MASK_AFP;
+ }
+ if (env->cregs[0] & CR0_VECTOR) {
+ *flags |= FLAG_MASK_VECTOR;
+ }
}
/* PER bits from control register 9 */
QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
/* MMU defines */
-#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
-#define _ASCE_SUBSPACE 0x200 /* subspace group control */
-#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
-#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
-#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
-#define _ASCE_REAL_SPACE 0x20 /* real space control */
-#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
-#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
-#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
-#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
-#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
-#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
-
-#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
-#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
-#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
-#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
-#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
-#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
-#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
-#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
-#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
-
-#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
-#define _SEGMENT_ENTRY_FC 0x400 /* format control */
-#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
-#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
-
-#define VADDR_PX 0xff000 /* page index bits */
-
-#define _PAGE_RO 0x200 /* HW read-only bit */
-#define _PAGE_INVALID 0x400 /* HW invalid bit */
-#define _PAGE_RES0 0x800 /* bit must be zero */
+#define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
+#define ASCE_SUBSPACE 0x200 /* subspace group control */
+#define ASCE_PRIVATE_SPACE 0x100 /* private space control */
+#define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
+#define ASCE_SPACE_SWITCH 0x40 /* space switch event */
+#define ASCE_REAL_SPACE 0x20 /* real space control */
+#define ASCE_TYPE_MASK 0x0c /* asce table type mask */
+#define ASCE_TYPE_REGION1 0x0c /* region first table type */
+#define ASCE_TYPE_REGION2 0x08 /* region second table type */
+#define ASCE_TYPE_REGION3 0x04 /* region third table type */
+#define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
+#define ASCE_TABLE_LENGTH 0x03 /* region table length */
+
+#define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin */
+#define REGION_ENTRY_RO 0x200 /* region/segment protection bit */
+#define REGION_ENTRY_TF 0xc0 /* region/segment table offset */
+#define REGION_ENTRY_INV 0x20 /* invalid region table entry */
+#define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
+#define REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
+#define REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
+#define REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
+#define REGION_ENTRY_LENGTH 0x03 /* region third length */
+
+#define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */
+#define SEGMENT_ENTRY_FC 0x400 /* format control */
+#define SEGMENT_ENTRY_RO 0x200 /* page protection bit */
+#define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
+
+#define VADDR_PX 0xff000 /* page index bits */
+
+#define PAGE_RO 0x200 /* HW read-only bit */
+#define PAGE_INVALID 0x400 /* HW invalid bit */
+#define PAGE_RES0 0x800 /* bit must be zero */
#define SK_C (0x1 << 1)
#define SK_R (0x1 << 2)
/* SIGP order code mask corresponding to bit positions 56-63 */
#define SIGP_ORDER_MASK 0x000000ff
-/* from s390-virtio-ccw */
-#define MEM_SECTION_SIZE 0x10000000UL
-#define MAX_AVAIL_SLOTS 32
-
/* machine check interruption code */
/* subclasses */
return mcic;
}
+static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
+{
+ cpu_reset(cs);
+}
+
+static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
+{
+ S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
+
+ scc->cpu_reset(cs);
+}
+
+static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
+{
+ S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
+
+ scc->initial_cpu_reset(cs);
+}
+
+static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
+{
+ S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
+
+ scc->load_normal(cs);
+}
+
/* cpu.c */
-int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
-int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
void s390_crypto_reset(void);
-bool s390_get_squash_mcss(void);
-int s390_get_memslot_count(void);
int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
+void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
void s390_cmma_reset(void);
void s390_enable_css_support(S390CPU *cpu);
int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
/* cpu_models.c */
-void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+void s390_cpu_list(void);
#define cpu_list s390_cpu_list
void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
const S390FeatInit feat_init);
/* helper.c */
-#define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
-
#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
+#define CPU_RESOLVING_TYPE TYPE_S390_CPU
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
/* outside of target/s390x/ */
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
+typedef CPUS390XState CPUArchState;
+typedef S390CPU ArchCPU;
+
+#include "exec/cpu-all.h"
+
#endif
projects / qemu.git / blobdiff