#if defined (TARGET_PPC64)
/* PowerPC 64 definitions */
-typedef uint64_t ppc_gpr_t;
-#define TARGET_GPR_BITS 64
#define TARGET_LONG_BITS 64
-#define REGX "%016" PRIx64
#define TARGET_PAGE_BITS 12
#else /* defined (TARGET_PPC64) */
/* PowerPC 32 definitions */
-#if (HOST_LONG_BITS >= 64)
-/* When using 64 bits temporary registers,
- * we can use 64 bits GPR with no extra cost
- * It's even an optimization as this will prevent
- * the compiler to do unuseful masking in the micro-ops.
- */
-typedef uint64_t ppc_gpr_t;
-#define TARGET_GPR_BITS 64
-#define REGX "%08" PRIx64
-#else /* (HOST_LONG_BITS >= 64) */
-typedef uint32_t ppc_gpr_t;
-#define TARGET_GPR_BITS 32
-#define REGX "%08" PRIx32
-#endif /* (HOST_LONG_BITS >= 64) */
-
#define TARGET_LONG_BITS 32
#if defined(TARGET_PPCEMB)
#include "cpu-defs.h"
+#define REGX "%016" PRIx64
#define ADDRX TARGET_FMT_lx
#define PADDRX TARGET_FMT_plx
void (*hea_read)(void *opaque, int spr_num);
void (*hea_write)(void *opaque, int spr_num);
#endif
- const unsigned char *name;
+ const char *name;
};
/* Altivec registers (128 bits) */
/*****************************************************************************/
/* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
+#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_SHV 60 /* hypervisor state hflags */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define msr_thv ((env->msr >> MSR_THV) & 1)
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr ((env->msr >> MSR_VR) & 1)
-#define msr_spe ((env->msr >> MSR_SE) & 1)
+#define msr_spe ((env->msr >> MSR_SPE) & 1)
#define msr_ap ((env->msr >> MSR_AP) & 1)
#define msr_sa ((env->msr >> MSR_SA) & 1)
#define msr_key ((env->msr >> MSR_KEY) & 1)
/* First are the most commonly used resources
* during translated code execution
*/
-#if (HOST_LONG_BITS == 32)
- /* temporary fixed-point registers
- * used to emulate 64 bits registers on 32 bits hosts
- */
- uint64_t t0, t1, t2;
+#if TARGET_LONG_BITS > HOST_LONG_BITS
+ target_ulong t0, t1;
+#endif
+ /* XXX: this is a temporary workaround for i386. cf translate.c comment */
+#if (TARGET_LONG_BITS > HOST_LONG_BITS) || defined(HOST_I386)
+ target_ulong t2;
#endif
- ppc_avr_t avr0, avr1, avr2;
/* general purpose registers */
- ppc_gpr_t gpr[32];
+ target_ulong gpr[32];
#if !defined(TARGET_PPC64)
/* Storage for GPR MSB, used by the SPE extension */
- ppc_gpr_t gprh[32];
+ target_ulong gprh[32];
#endif
/* LR */
target_ulong lr;
/* CTR */
target_ulong ctr;
/* condition register */
- uint8_t crf[8];
+ uint32_t crf[8];
/* XER */
- /* XXX: We use only 5 fields, but we want to keep the structure aligned */
- uint8_t xer[8];
+ target_ulong xer;
/* Reservation address */
target_ulong reserve;
/* machine state register */
target_ulong msr;
/* temporary general purpose registers */
- ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
+ target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
/* Floating point execution context */
- /* temporary float registers */
- float64 ft0;
- float64 ft1;
- float64 ft2;
float_status fp_status;
/* floating point registers */
float64 fpr[32];
CPU_COMMON
- int halted; /* TRUE if the CPU is in suspend state */
-
int access_type; /* when a memory exception occurs, the access
type is stored here */
ppc_avr_t avr[32];
uint32_t vscr;
/* SPE registers */
- ppc_gpr_t spe_acc;
+ target_ulong spe_acc;
float_status spe_status;
uint32_t spe_fscr;
int bfd_mach;
uint32_t flags;
- int exception_index;
int error_code;
- int interrupt_request;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
/* This is the IRQ controller, which is implementation dependant
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
- jmp_buf jmp_env;
- int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */
/*****************************************************************************/
CPUPPCState *cpu_ppc_init (const char *cpu_model);
+void ppc_translate_init(void);
int cpu_ppc_exec (CPUPPCState *s);
void cpu_ppc_close (CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
void do_interrupt (CPUPPCState *env);
void ppc_hw_interrupt (CPUPPCState *env);
-void cpu_loop_exit (void);
void dump_stack (CPUPPCState *env);
#endif
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
#endif /* !defined(CONFIG_USER_ONLY) */
-target_ulong ppc_load_xer (CPUPPCState *env);
-void ppc_store_xer (CPUPPCState *env, target_ulong value);
void ppc_store_msr (CPUPPCState *env, target_ulong value);
void cpu_ppc_reset (void *opaque);
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
-const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
+const ppc_def_t *cpu_ppc_find_by_name (const char *name);
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
/* Time-base and decrementer management */
#endif
#endif
+static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
+{
+ uint64_t gprv;
+
+ gprv = env->gpr[gprn];
+#if !defined(TARGET_PPC64)
+ if (env->flags & POWERPC_FLAG_SPE) {
+ /* If the CPU implements the SPE extension, we have to get the
+ * high bits of the GPR from the gprh storage area
+ */
+ gprv &= 0xFFFFFFFFULL;
+ gprv |= (uint64_t)env->gprh[gprn] << 32;
+ }
+#endif
+
+ return gprv;
+}
+
/* Device control registers */
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
+#define CPU_SAVE_VERSION 3
+
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
return env->mmu_idx;
}
+#if defined(CONFIG_USER_ONLY)
+static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+{
+ int i;
+ if (newsp)
+ env->gpr[1] = newsp;
+ for (i = 7; i < 32; i++)
+ env->gpr[i] = 0;
+}
+#endif
+
#include "cpu-all.h"
+#include "exec-all.h"
/*****************************************************************************/
-/* Registers definitions */
-#define XER_SO 31
-#define XER_OV 30
-#define XER_CA 29
-#define XER_CMP 8
-#define XER_BC 0
-#define xer_so env->xer[4]
-#define xer_ov env->xer[6]
-#define xer_ca env->xer[2]
-#define xer_cmp env->xer[1]
-#define xer_bc env->xer[0]
+/* CRF definitions */
+#define CRF_LT 3
+#define CRF_GT 2
+#define CRF_EQ 1
+#define CRF_SO 0
+#define CRF_CH (1 << 4)
+#define CRF_CL (1 << 3)
+#define CRF_CH_OR_CL (1 << 2)
+#define CRF_CH_AND_CL (1 << 1)
+
+/* XER definitions */
+#define XER_SO 31
+#define XER_OV 30
+#define XER_CA 29
+#define XER_CMP 8
+#define XER_BC 0
+#define xer_so ((env->xer >> XER_SO) & 1)
+#define xer_ov ((env->xer >> XER_OV) & 1)
+#define xer_ca ((env->xer >> XER_CA) & 1)
+#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
+#define xer_bc ((env->xer >> XER_BC) & 0x7F)
/* SPR definitions */
#define SPR_MQ (0x000)
#define SPR_440_CCR1 (0x378)
#define SPR_DCRIPR (0x37B)
#define SPR_PPR (0x380)
+#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
+#define SPR_750_GQR1 (0x391)
#define SPR_440_DNV1 (0x391)
+#define SPR_750_GQR2 (0x392)
#define SPR_440_DNV2 (0x392)
+#define SPR_750_GQR3 (0x393)
#define SPR_440_DNV3 (0x393)
+#define SPR_750_GQR4 (0x394)
#define SPR_440_DTV0 (0x394)
+#define SPR_750_GQR5 (0x395)
#define SPR_440_DTV1 (0x395)
+#define SPR_750_GQR6 (0x396)
#define SPR_440_DTV2 (0x396)
+#define SPR_750_GQR7 (0x397)
#define SPR_440_DTV3 (0x397)
+#define SPR_750_THRM4 (0x398)
+#define SPR_750CL_HID2 (0x398)
#define SPR_440_DVLIM (0x398)
+#define SPR_750_WPAR (0x399)
#define SPR_440_IVLIM (0x399)
+#define SPR_750_DMAU (0x39A)
+#define SPR_750_DMAL (0x39B)
#define SPR_440_RSTCFG (0x39B)
#define SPR_BOOKE_DCDBTRL (0x39C)
#define SPR_BOOKE_DCDBTRH (0x39D)
#define SPR_40x_EVPR (0x3D6)
#define SPR_L3PM (0x3D7)
#define SPR_403_CDBCR (0x3D7)
-#define SPR_L3OHCR (0x3D8)
+#define SPR_L3ITCR0 (0x3D8)
#define SPR_TCR (0x3D8)
#define SPR_40x_TSR (0x3D8)
#define SPR_IBR (0x3DA)
#define SPR_40x_SRR2 (0x3DE)
#define SPR_SER (0x3DF)
#define SPR_40x_SRR3 (0x3DF)
-#define SPR_L3ITCR0 (0x3E8)
+#define SPR_L3OHCR (0x3E8)
#define SPR_L3ITCR1 (0x3E9)
#define SPR_L3ITCR2 (0x3EA)
#define SPR_L3ITCR3 (0x3EB)
#define SPR_Exxx_L1CSR0 (0x3F2)
#define SPR_ICTRL (0x3F3)
#define SPR_HID2 (0x3F3)
+#define SPR_750CL_HID4 (0x3F3)
#define SPR_Exxx_L1CSR1 (0x3F3)
#define SPR_440_DBDR (0x3F3)
#define SPR_LDSTDB (0x3F4)
+#define SPR_750_TDCL (0x3F4)
#define SPR_40x_IAC1 (0x3F4)
#define SPR_MMUCSR0 (0x3F4)
#define SPR_DABR (0x3F5)
#define SPR_MSSCR0 (0x3F6)
#define SPR_970_HID5 (0x3F6)
#define SPR_MSSSR0 (0x3F7)
+#define SPR_MSSCR1 (0x3F7)
#define SPR_DABRX (0x3F7)
#define SPR_40x_DAC2 (0x3F7)
#define SPR_MMUCFG (0x3F7)
#define SPR_LDSTCR (0x3F8)
#define SPR_L2PMCR (0x3F8)
-#define SPR_750_HID2 (0x3F8)
+#define SPR_750FX_HID2 (0x3F8)
#define SPR_620_BUSCSR (0x3F8)
#define SPR_Exxx_L1FINV0 (0x3F8)
#define SPR_L2CR (0x3F9)
#define SPR_620_L2CR (0x3F9)
#define SPR_L3CR (0x3FA)
+#define SPR_750_TDCH (0x3FA)
#define SPR_IABR2 (0x3FA)
#define SPR_40x_DCCR (0x3FA)
#define SPR_620_L2SR (0x3FA)
/*****************************************************************************/
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->nip = tb->pc;
+}
+
+static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->nip;
+ *cs_base = 0;
+ *flags = env->hflags;
+}
+
#endif /* !defined (__CPU_PPC_H__) */
projects / qemu.git / blobdiff