target-ppc: convert dcbz instruction to TCG

[qemu.git] / target-ppc / exec.h

diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index 5abcee052250bb362828bbb09f3fd5d7dff2883e..67cb8b43770d757f1318873f35ca11e5b2ec7127 100644 (file)
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -37,30 +37,13 @@ register struct CPUPPCState *env asm(AREG0);
 #define T0 (env->t0)
 #define T1 (env->t1)
 #define T2 (env->t2)
+#define TDX "%016" PRIx64
 #else
-register unsigned long T0 asm(AREG1);
-register unsigned long T1 asm(AREG2);
-register unsigned long T2 asm(AREG3);
+register target_ulong T0 asm(AREG1);
+register target_ulong T1 asm(AREG2);
+register target_ulong T2 asm(AREG3);
+#define TDX "%016lx"
 #endif
-/* We may, sometime, need 64 bits registers on 32 bits target */
-#if TARGET_GPR_BITS > HOST_LONG_BITS
-/* no registers can be used */
-#define T0_64 (env->t0)
-#define T1_64 (env->t1)
-#define T2_64 (env->t2)
-#else
-#define T0_64 T0
-#define T1_64 T1
-#define T2_64 T2
-#endif
-/* Provision for Altivec */
-#define AVR0 (env->avr0)
-#define AVR1 (env->avr1)
-#define AVR2 (env->avr2)
-
-#define FT0 (env->ft0)
-#define FT1 (env->ft1)
-#define FT2 (env->ft2)
 
 #if defined (DEBUG_OP)
 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
@@ -94,11 +77,11 @@ static always_inline target_ulong rotl64 (target_ulong i, int n)
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-void do_raise_exception_err (uint32_t exception, int error_code);
-void do_raise_exception (uint32_t exception);
+void raise_exception_err (CPUState *env, int exception, int error_code);
+void raise_exception (CPUState *env, int exception);
 
 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
-                          int rw, int access_type, int check_BATs);
+                          int rw, int access_type);
 
 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
                        target_ulong pte0, target_ulong pte1);