* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "vl.h"
+#include "hw.h"
+#include "i2c.h"
+#include "omap.h"
struct omap_i2c_s {
- target_phys_addr_t base;
+ MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
- i2c_slave slave;
i2c_bus *bus;
+ uint8_t revision;
uint8_t mask;
uint16_t stat;
uint16_t dma;
uint16_t test;
};
+#define OMAP2_INTR_REV 0x34
+#define OMAP2_GC_REV 0x34
+
static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
{
qemu_set_irq(s->irq, s->stat & s->mask);
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
}
-/* These are only stubs now. */
-static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event)
-{
- struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-
- if ((~s->control >> 15) & 1) /* I2C_EN */
- return;
-
- switch (event) {
- case I2C_START_SEND:
- case I2C_START_RECV:
- s->stat |= 1 << 9; /* AAS */
- break;
- case I2C_FINISH:
- s->stat |= 1 << 2; /* ARDY */
- break;
- case I2C_NACK:
- s->stat |= 1 << 1; /* NACK */
- break;
- }
-
- omap_i2c_interrupts_update(s);
-}
-
-static int omap_i2c_rx(i2c_slave *i2c)
-{
- struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
- uint8_t ret = 0;
-
- if ((~s->control >> 15) & 1) /* I2C_EN */
- return -1;
-
- if (s->txlen)
- ret = s->fifo >> ((-- s->txlen) << 3) & 0xff;
- else
- s->stat |= 1 << 10; /* XUDF */
- s->stat |= 1 << 4; /* XRDY */
-
- omap_i2c_interrupts_update(s);
- return ret;
-}
-
-static int omap_i2c_tx(i2c_slave *i2c, uint8_t data)
-{
- struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-
- if ((~s->control >> 15) & 1) /* I2C_EN */
- return 1;
-
- if (s->rxlen < 4)
- s->fifo |= data << ((s->rxlen ++) << 3);
- else
- s->stat |= 1 << 11; /* ROVR */
- s->stat |= 1 << 3; /* RRDY */
-
- omap_i2c_interrupts_update(s);
- return 1;
-}
-
static void omap_i2c_fifo_run(struct omap_i2c_s *s)
{
int ack = 1;
i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
+ s->txlen = 0;
} else if ((s->control >> 9) & 1) { /* TRX */
while (ack && s->txlen)
ack = (i2c_send(s->bus,
}
if (ack && s->count_cur)
s->stat |= 1 << 4; /* XRDY */
+ else
+ s->stat &= ~(1 << 4); /* XRDY */
if (!s->count_cur) {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
}
if (s->rxlen)
s->stat |= 1 << 3; /* RRDY */
+ else
+ s->stat &= ~(1 << 3); /* RRDY */
}
if (!s->count_cur) {
if ((s->control >> 1) & 1) { /* STP */
i2c_end_transfer(s->bus);
s->control &= ~(1 << 1); /* STP */
s->count_cur = s->count;
+ s->txlen = 0;
} else {
s->stat |= 1 << 2; /* ARDY */
s->control &= ~(1 << 10); /* MST */
static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
- int offset = addr - s->base;
+ int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
switch (offset) {
case 0x00: /* I2C_REV */
- /* TODO: set a value greater or equal to real hardware */
- return 0x11; /* REV */
+ return s->revision; /* REV */
case 0x04: /* I2C_IE */
return s->mask;
return s->stat | (i2c_bus_busy(s->bus) << 12);
case 0x0c: /* I2C_IV */
+ if (s->revision >= OMAP2_INTR_REV)
+ break;
ret = ffs(s->stat & s->mask);
if (ret)
s->stat ^= 1 << (ret - 1);
omap_i2c_interrupts_update(s);
return ret;
+ case 0x10: /* I2C_SYSS */
+ return (s->control >> 15) & 1; /* I2C_EN */
+
case 0x14: /* I2C_BUF */
return s->dma;
if (s->rxlen > 2)
s->fifo >>= 16;
s->rxlen -= 2;
- } else
- /* XXX: remote access (qualifier) error - what's that? */;
+ } else {
+ /* XXX: remote access (qualifier) error - what's that? */
+ }
if (!s->rxlen) {
- s->stat |= ~(1 << 3); /* RRDY */
+ s->stat &= ~(1 << 3); /* RRDY */
if (((s->control >> 10) & 1) && /* MST */
((~s->control >> 9) & 1)) { /* TRX */
s->stat |= 1 << 2; /* ARDY */
omap_i2c_interrupts_update(s);
return ret;
+ case 0x20: /* I2C_SYSC */
+ return 0;
+
case 0x24: /* I2C_CON */
return s->control;
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
- int offset = addr - s->base;
+ int offset = addr & OMAP_MPUI_REG_MASK;
int nack;
switch (offset) {
case 0x00: /* I2C_REV */
- case 0x08: /* I2C_STAT */
case 0x0c: /* I2C_IV */
- OMAP_BAD_REG(addr);
+ case 0x10: /* I2C_SYSS */
+ OMAP_RO_REG(addr);
return;
case 0x04: /* I2C_IE */
- s->mask = value & 0x1f;
+ s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
+ break;
+
+ case 0x08: /* I2C_STAT */
+ if (s->revision < OMAP2_INTR_REV) {
+ OMAP_RO_REG(addr);
+ return;
+ }
+
+ /* RRDY and XRDY are reset by hardware. (in all versions???) */
+ s->stat &= ~(value & 0x27);
+ omap_i2c_interrupts_update(s);
break;
case 0x14: /* I2C_BUF */
omap_i2c_interrupts_update(s);
break;
+ case 0x20: /* I2C_SYSC */
+ if (s->revision < OMAP2_INTR_REV) {
+ OMAP_BAD_REG(addr);
+ return;
+ }
+
+ if (value & 2)
+ omap_i2c_reset(s);
+ break;
+
case 0x24: /* I2C_CON */
- s->control = value & 0xcf07;
+ s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */
- omap_i2c_reset(s);
+ if (s->revision < OMAP2_INTR_REV)
+ omap_i2c_reset(s);
break;
}
- if (~value & (1 << 10)) { /* MST */
- printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
+ if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
+ fprintf(stderr, "%s: I^2C slave mode not supported\n",
+ __FUNCTION__);
break;
}
- if (value & (1 << 9)) { /* XA */
- printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
+ if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
+ fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
+ __FUNCTION__);
break;
}
- if (value & (1 << 0)) { /* STT */
+ if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
(~value >> 9) & 1); /* TRX */
s->stat |= nack << 1; /* NACK */
s->control &= ~(1 << 0); /* STT */
+ s->fifo = 0;
if (nack)
s->control &= ~(1 << 1); /* STP */
- else
+ else {
+ s->count_cur = s->count;
omap_i2c_fifo_run(s);
+ }
omap_i2c_interrupts_update(s);
}
break;
case 0x28: /* I2C_OA */
s->addr[0] = value & 0x3ff;
- i2c_set_slave_address(&s->slave, value & 0x7f);
break;
case 0x2c: /* I2C_SA */
break;
case 0x3c: /* I2C_SYSTEST */
- s->test = value & 0xf00f;
+ s->test = value & 0xf80f;
+ if (value & (1 << 11)) /* SBB */
+ if (s->revision >= OMAP2_INTR_REV) {
+ s->stat |= 0x3f;
+ omap_i2c_interrupts_update(s);
+ }
if (value & (1 << 15)) /* ST_EN */
- printf("%s: System Test not supported\n", __FUNCTION__);
+ fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
break;
default:
}
}
-static CPUReadMemoryFunc *omap_i2c_readfn[] = {
- omap_badwidth_read16,
- omap_i2c_read,
- omap_badwidth_read16,
-};
+static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
+ int offset = addr & OMAP_MPUI_REG_MASK;
-static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
- omap_badwidth_write16,
- omap_i2c_write,
- omap_i2c_write, /* TODO: Only the last fifo write can be 8 bit. */
+ switch (offset) {
+ case 0x1c: /* I2C_DATA */
+ if (s->txlen > 2) {
+ /* XXX: remote access (qualifier) error - what's that? */
+ break;
+ }
+ s->fifo <<= 8;
+ s->txlen += 1;
+ s->fifo |= value & 0xff;
+ s->stat &= ~(1 << 10); /* XUDF */
+ if (s->txlen > 2)
+ s->stat &= ~(1 << 4); /* XRDY */
+ omap_i2c_fifo_run(s);
+ omap_i2c_interrupts_update(s);
+ break;
+
+ default:
+ OMAP_BAD_REG(addr);
+ return;
+ }
+}
+
+static const MemoryRegionOps omap_i2c_ops = {
+ .old_mmio = {
+ .read = {
+ omap_badwidth_read16,
+ omap_i2c_read,
+ omap_badwidth_read16,
+ },
+ .write = {
+ omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
+ omap_i2c_write,
+ omap_badwidth_write16,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
- qemu_irq irq, qemu_irq *dma, omap_clk clk)
+struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
+ qemu_irq *dma,
+ omap_clk clk)
+{
+ struct omap_i2c_s *s = (struct omap_i2c_s *)
+ g_malloc0(sizeof(struct omap_i2c_s));
+
+ /* TODO: set a value greater or equal to real hardware */
+ s->revision = 0x11;
+ s->irq = irq;
+ s->drq[0] = dma[0];
+ s->drq[1] = dma[1];
+ s->bus = i2c_init_bus(NULL, "i2c");
+ omap_i2c_reset(s);
+
+ memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
+
+ return s;
+}
+
+struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
+ qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
{
- int iomemtype;
struct omap_i2c_s *s = (struct omap_i2c_s *)
- qemu_mallocz(sizeof(struct omap_i2c_s));
+ g_malloc0(sizeof(struct omap_i2c_s));
- s->base = base;
+ s->revision = 0x34;
s->irq = irq;
s->drq[0] = dma[0];
s->drq[1] = dma[1];
- s->slave.event = omap_i2c_event;
- s->slave.recv = omap_i2c_rx;
- s->slave.send = omap_i2c_tx;
- s->bus = i2c_init_bus();
+ s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
- iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
- omap_i2c_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c",
+ omap_l4_region_size(ta, 0));
+ omap_l4_attach(ta, 0, &s->iomem);
return s;
}
projects / qemu.git / blobdiff