#include "sysemu.h"
#include "block.h"
#include "boards.h"
-
-extern int loglevel;
-extern FILE *logfile;
+#include "qemu-log.h"
+#include "loader.h"
+#include "blockdev.h"
+#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin"
-#undef BIOS_SIZE
#define BIOS_SIZE (2048 * 1024)
#define KERNEL_LOAD_ADDR 0x00000000
*/
typedef struct ref405ep_fpga_t ref405ep_fpga_t;
struct ref405ep_fpga_t {
- uint32_t base;
uint8_t reg0;
uint8_t reg1;
};
uint32_t ret;
fpga = opaque;
- addr -= fpga->base;
switch (addr) {
case 0x0:
ret = fpga->reg0;
ref405ep_fpga_t *fpga;
fpga = opaque;
- addr -= fpga->base;
switch (addr) {
case 0x0:
/* Read only */
static void ref405ep_fpga_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
- ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
- ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
+ ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
+ ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
+ ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
}
-static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
+static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
&ref405ep_fpga_readb,
&ref405ep_fpga_readw,
&ref405ep_fpga_readl,
};
-static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
+static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
&ref405ep_fpga_writeb,
&ref405ep_fpga_writew,
&ref405ep_fpga_writel,
ref405ep_fpga_t *fpga;
int fpga_memory;
- fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
- if (fpga != NULL) {
- fpga->base = base;
- fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
- ref405ep_fpga_write, fpga);
- cpu_register_physical_memory(base, 0x00000100, fpga_memory);
- ref405ep_fpga_reset(fpga);
- qemu_register_reset(&ref405ep_fpga_reset, fpga);
- }
+ fpga = g_malloc0(sizeof(ref405ep_fpga_t));
+ fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
+ ref405ep_fpga_write, fpga,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x00000100, fpga_memory);
+ qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
-static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+static void ref405ep_init (ram_addr_t ram_size,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
- char buf[1024];
+ char *filename;
ppc4xx_bd_info_t bd;
CPUPPCState *env;
qemu_irq *pic;
- ram_addr_t sram_offset, bios_offset, bdloc;
+ MemoryRegion *bios;
+ ram_addr_t sram_offset, bdloc;
+ MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
- target_ulong sram_size, bios_size;
+ target_ulong sram_size;
+ long bios_size;
//int phy_addr = 0;
//static int phy_addr = 1;
- target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
+ target_ulong kernel_base, initrd_base;
+ long kernel_size, initrd_size;
int linux_boot;
int fl_idx, fl_sectors, len;
- int ppc_boot_device = boot_device[0];
- int index;
+ DriveInfo *dinfo;
/* XXX: fix this */
- ram_bases[0] = 0x00000000;
+ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x08000000;
+ memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
ram_size = 128 * 1024 * 1024;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
+ env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
+ sram_size = 512 * 1024;
+ sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
#ifdef DEBUG_BOARD_INIT
printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
#endif
- sram_size = 512 * 1024;
cpu_register_physical_memory(0xFFF00000, sram_size,
sram_offset | IO_MEM_RAM);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
printf("%s: register BIOS\n", __func__);
#endif
- bios_offset = sram_offset + sram_size;
fl_idx = 0;
#ifdef USE_FLASH_BIOS
- index = drive_get_index(IF_PFLASH, 0, fl_idx);
- if (index != -1) {
- bios_size = bdrv_getlength(drives_table[index].bdrv);
+ dinfo = drive_get(IF_PFLASH, 0, fl_idx);
+ if (dinfo) {
+ bios_size = bdrv_getlength(dinfo->bdrv);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " ADDRX " at offset %08lx "
- " addr " ADDRX " '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
- bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
+ printf("Register parallel flash %d size %lx"
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
+ bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
- drives_table[index].bdrv, 65536, fl_sectors, 1,
- 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
+ pflash_cfi02_register((uint32_t)(-bios_size),
+ NULL, "ef405ep.bios", bios_size,
+ dinfo->bdrv, 65536, fl_sectors, 1,
+ 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
+ 1);
fl_idx++;
} else
#endif
#ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n");
#endif
+ bios = g_new(MemoryRegion, 1);
+ memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
- snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
- bios_size = load_image(buf, phys_ram_base + bios_offset);
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
+ fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
+ bios_name);
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(get_system_memory(),
+ (uint32_t)(-bios_size), bios);
}
- bios_offset += bios_size;
/* Register FPGA */
#ifdef DEBUG_BOARD_INIT
printf("%s: register FPGA\n", __func__);
env->gpr[3] = bdloc;
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
- kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
+ kernel_size = load_image_targphys(kernel_filename, kernel_base,
+ ram_size - kernel_base);
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
- printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
- " %02x %02x %02x %02x\n", kernel_size, kernel_base,
- *(char *)(phys_ram_base + kernel_base),
- *(char *)(phys_ram_base + kernel_base + 1),
- *(char *)(phys_ram_base + kernel_base + 2),
- *(char *)(phys_ram_base + kernel_base + 3));
+ printf("Load kernel size %ld at " TARGET_FMT_lx,
+ kernel_size, kernel_base);
/* load initrd */
if (initrd_filename) {
initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image(initrd_filename,
- phys_ram_base + initrd_base);
+ initrd_size = load_image_targphys(initrd_filename, initrd_base,
+ ram_size - initrd_base);
if (initrd_size < 0) {
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
}
env->gpr[4] = initrd_base;
env->gpr[5] = initrd_size;
- ppc_boot_device = 'm';
if (kernel_cmdline != NULL) {
len = strlen(kernel_cmdline);
bdloc -= ((len + 255) & ~255);
- memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
+ cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
env->gpr[6] = bdloc;
env->gpr[7] = bdloc + len;
} else {
#ifdef DEBUG_BOARD_INIT
printf("%s: Done\n", __func__);
#endif
- printf("bdloc %016lx %s\n",
- (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
+ printf("bdloc %016lx\n", (unsigned long)bdloc);
}
-QEMUMachine ref405ep_machine = {
- "ref405ep",
- "ref405ep",
- ref405ep_init,
- (128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE) | RAMSIZE_FIXED,
+static QEMUMachine ref405ep_machine = {
+ .name = "ref405ep",
+ .desc = "ref405ep",
+ .init = ref405ep_init,
};
/*****************************************************************************/
*/
typedef struct taihu_cpld_t taihu_cpld_t;
struct taihu_cpld_t {
- uint32_t base;
uint8_t reg0;
uint8_t reg1;
};
uint32_t ret;
cpld = opaque;
- addr -= cpld->base;
switch (addr) {
case 0x0:
ret = cpld->reg0;
taihu_cpld_t *cpld;
cpld = opaque;
- addr -= cpld->base;
switch (addr) {
case 0x0:
/* Read only */
taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
}
-static CPUReadMemoryFunc *taihu_cpld_read[] = {
+static CPUReadMemoryFunc * const taihu_cpld_read[] = {
&taihu_cpld_readb,
&taihu_cpld_readw,
&taihu_cpld_readl,
};
-static CPUWriteMemoryFunc *taihu_cpld_write[] = {
+static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
&taihu_cpld_writeb,
&taihu_cpld_writew,
&taihu_cpld_writel,
taihu_cpld_t *cpld;
int cpld_memory;
- cpld = qemu_mallocz(sizeof(taihu_cpld_t));
- if (cpld != NULL) {
- cpld->base = base;
- cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
- taihu_cpld_write, cpld);
- cpu_register_physical_memory(base, 0x00000100, cpld_memory);
- taihu_cpld_reset(cpld);
- qemu_register_reset(&taihu_cpld_reset, cpld);
- }
+ cpld = g_malloc0(sizeof(taihu_cpld_t));
+ cpld_memory = cpu_register_io_memory(taihu_cpld_read,
+ taihu_cpld_write, cpld,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x00000100, cpld_memory);
+ qemu_register_reset(&taihu_cpld_reset, cpld);
}
-static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+static void taihu_405ep_init(ram_addr_t ram_size,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
- char buf[1024];
- CPUPPCState *env;
+ char *filename;
qemu_irq *pic;
- ram_addr_t bios_offset;
+ MemoryRegion *bios;
+ MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
- target_ulong bios_size;
- target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
+ long bios_size;
+ target_ulong kernel_base, initrd_base;
+ long kernel_size, initrd_size;
int linux_boot;
int fl_idx, fl_sectors;
- int ppc_boot_device = boot_device[0];
- int index;
+ DriveInfo *dinfo;
/* RAM is soldered to the board so the size cannot be changed */
- ram_bases[0] = 0x00000000;
+ memory_region_init_ram(&ram_memories[0], NULL,
+ "taihu_405ep.ram-0", 0x04000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
+ memory_region_init_ram(&ram_memories[1], NULL,
+ "taihu_405ep.ram-1", 0x04000000);
ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
+ ram_size = 0x08000000;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
- kernel_filename == NULL ? 0 : 1);
+ ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
+ kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
printf("%s: register BIOS\n", __func__);
#endif
fl_idx = 0;
#if defined(USE_FLASH_BIOS)
- index = drive_get_index(IF_PFLASH, 0, fl_idx);
- if (index != -1) {
- bios_size = bdrv_getlength(drives_table[index].bdrv);
+ dinfo = drive_get(IF_PFLASH, 0, fl_idx);
+ if (dinfo) {
+ bios_size = bdrv_getlength(dinfo->bdrv);
/* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " ADDRX " at offset %08lx "
- " addr " ADDRX " '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
- bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
+ printf("Register parallel flash %d size %lx"
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
+ bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
- drives_table[index].bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
+ pflash_cfi02_register((uint32_t)(-bios_size),
+ NULL, "taihu_405ep.bios", bios_size,
+ dinfo->bdrv, 65536, fl_sectors, 1,
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
+ 1);
fl_idx++;
} else
#endif
#endif
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
- snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
- bios_size = load_image(buf, phys_ram_base + bios_offset);
+ bios = g_new(MemoryRegion, 1);
+ memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
+ fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
+ bios_name);
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size),
+ bios);
}
- bios_offset += bios_size;
/* Register Linux flash */
- index = drive_get_index(IF_PFLASH, 0, fl_idx);
- if (index != -1) {
- bios_size = bdrv_getlength(drives_table[index].bdrv);
+ dinfo = drive_get(IF_PFLASH, 0, fl_idx);
+ if (dinfo) {
+ bios_size = bdrv_getlength(dinfo->bdrv);
/* XXX: should check that size is 32MB */
bios_size = 32 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " ADDRX " at offset %08lx "
- " addr " ADDRX " '%s'\n",
- fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
- bdrv_get_device_name(drives_table[index].bdrv));
+ printf("Register parallel flash %d size %lx"
+ " at addr " TARGET_FMT_lx " '%s'\n",
+ fl_idx, bios_size, (target_ulong)0xfc000000,
+ bdrv_get_device_name(dinfo->bdrv));
#endif
- pflash_cfi02_register(0xfc000000, bios_offset,
- drives_table[index].bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
+ pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
+ dinfo->bdrv, 65536, fl_sectors, 1,
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
+ 1);
fl_idx++;
}
/* Register CLPD & LCD display */
#endif
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
- kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
+ kernel_size = load_image_targphys(kernel_filename, kernel_base,
+ ram_size - kernel_base);
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
/* load initrd */
if (initrd_filename) {
initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image(initrd_filename,
- phys_ram_base + initrd_base);
+ initrd_size = load_image_targphys(initrd_filename, initrd_base,
+ ram_size - initrd_base);
if (initrd_size < 0) {
fprintf(stderr,
"qemu: could not load initial ram disk '%s'\n",
initrd_base = 0;
initrd_size = 0;
}
- ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
#endif
}
-QEMUMachine taihu_machine = {
- "taihu",
- "taihu",
- taihu_405ep_init,
- (128 * 1024 * 1024 + 4096 + BIOS_SIZE + 32 * 1024 * 1024) | RAMSIZE_FIXED,
+static QEMUMachine taihu_machine = {
+ .name = "taihu",
+ .desc = "taihu",
+ .init = taihu_405ep_init,
};
+
+static void ppc405_machine_init(void)
+{
+ qemu_register_machine(&ref405ep_machine);
+ qemu_register_machine(&taihu_machine);
+}
+
+machine_init(ppc405_machine_init);
projects / qemu.git / blobdiff