};
/* MFMC0 opcodes */
-#define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
+#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
enum {
OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
-#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
+
+enum {
+ OPC_MFC2 = (0x00 << 21) | OPC_CP2,
+ OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
+ OPC_CFC2 = (0x02 << 21) | OPC_CP2,
+ OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
+ OPC_MTC2 = (0x04 << 21) | OPC_CP2,
+ OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
+ OPC_CTC2 = (0x06 << 21) | OPC_CP2,
+ OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
+ OPC_BC2 = (0x08 << 21) | OPC_CP2,
+};
+
+#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
+
+enum {
+ OPC_LWXC1 = 0x00 | OPC_CP3,
+ OPC_LDXC1 = 0x01 | OPC_CP3,
+ OPC_LUXC1 = 0x05 | OPC_CP3,
+ OPC_SWXC1 = 0x08 | OPC_CP3,
+ OPC_SDXC1 = 0x09 | OPC_CP3,
+ OPC_SUXC1 = 0x0D | OPC_CP3,
+ OPC_PREFX = 0x0F | OPC_CP3,
+ OPC_ALNV_PS = 0x1E | OPC_CP3,
+ OPC_MADD_S = 0x20 | OPC_CP3,
+ OPC_MADD_D = 0x21 | OPC_CP3,
+ OPC_MADD_PS = 0x26 | OPC_CP3,
+ OPC_MSUB_S = 0x28 | OPC_CP3,
+ OPC_MSUB_D = 0x29 | OPC_CP3,
+ OPC_MSUB_PS = 0x2E | OPC_CP3,
+ OPC_NMADD_S = 0x30 | OPC_CP3,
+ OPC_NMADD_D = 0x32 | OPC_CP3,
+ OPC_NMADD_PS= 0x36 | OPC_CP3,
+ OPC_NMSUB_S = 0x38 | OPC_CP3,
+ OPC_NMSUB_D = 0x39 | OPC_CP3,
+ OPC_NMSUB_PS= 0x3E | OPC_CP3,
+};
+
const unsigned char *regnames[] =
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
-#ifdef MIPS_USES_FPU
-
static const char *fregnames[] =
{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
FOP_CONDS(d)
FOP_CONDS(s)
-#endif /* MIPS_USES_FPU */
-
typedef struct DisasContext {
struct TranslationBlock *tb;
target_ulong pc, saved_pc;
}
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
OP_LD_TABLE(d);
OP_LD_TABLE(dl);
OP_LD_TABLE(dr);
OP_ST_TABLE(b);
OP_LD_TABLE(l);
OP_ST_TABLE(c);
-#ifdef MIPS_USES_FPU
OP_LD_TABLE(wc1);
OP_ST_TABLE(wc1);
OP_LD_TABLE(dc1);
OP_ST_TABLE(dc1);
-#endif
/* Load and store */
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
* memory access
*/
switch (opc) {
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_LD:
op_ldst(ld);
GEN_STORE_TN_REG(rt, T0);
opn = "sd";
break;
case OPC_SCD:
+ save_cpu_state(ctx, 1);
GEN_LOAD_REG_TN(T1, rt);
op_ldst(scd);
opn = "scd";
opn = "ll";
break;
case OPC_SC:
+ save_cpu_state(ctx, 1);
GEN_LOAD_REG_TN(T1, rt);
op_ldst(sc);
GEN_STORE_TN_REG(rt, T0);
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
}
-#ifdef MIPS_USES_FPU
-
/* Load and store */
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
int base, int16_t offset)
break;
default:
MIPS_INVAL("float load/store");
- generate_exception_err(ctx, EXCP_CpU, 1);
+ generate_exception(ctx, EXCP_RI);
return;
}
MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
}
-#endif /* MIPS_USES_FPU */
-
/* Arithmetic with immediate operand */
static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
int rs, int16_t imm)
MIPS_DEBUG("NOP");
return;
}
- if (opc == OPC_ADDI || opc == OPC_ADDIU ||
- opc == OPC_DADDI || opc == OPC_DADDIU ||
- opc == OPC_SLTI || opc == OPC_SLTIU)
+ uimm = (uint16_t)imm;
+ switch (opc) {
+ case OPC_ADDI:
+ case OPC_ADDIU:
+#ifdef TARGET_MIPS64
+ case OPC_DADDI:
+ case OPC_DADDIU:
+#endif
+ case OPC_SLTI:
+ case OPC_SLTIU:
uimm = (int32_t)imm; /* Sign extend to 32 bits */
- else
- uimm = (uint16_t)imm;
- if (opc != OPC_LUI) {
+ /* Fall through. */
+ case OPC_ANDI:
+ case OPC_ORI:
+ case OPC_XORI:
GEN_LOAD_REG_TN(T0, rs);
GEN_LOAD_IMM_TN(T1, uimm);
- } else {
- uimm = uimm << 16;
+ break;
+ case OPC_LUI:
+ uimm <<= 16;
GEN_LOAD_IMM_TN(T0, uimm);
+ break;
+ case OPC_SLL:
+ case OPC_SRA:
+ case OPC_SRL:
+#ifdef TARGET_MIPS64
+ case OPC_DSLL:
+ case OPC_DSRA:
+ case OPC_DSRL:
+ case OPC_DSLL32:
+ case OPC_DSRA32:
+ case OPC_DSRL32:
+#endif
+ uimm &= 0x1f;
+ GEN_LOAD_REG_TN(T0, rs);
+ GEN_LOAD_IMM_TN(T1, uimm);
+ break;
}
switch (opc) {
case OPC_ADDI:
gen_op_add();
opn = "addiu";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DADDI:
save_cpu_state(ctx, 1);
gen_op_daddo();
opn = "sra";
break;
case OPC_SRL:
- if ((ctx->opcode >> 21) & 1) {
- gen_op_rotr();
- opn = "rotr";
- } else {
+ switch ((ctx->opcode >> 21) & 0x1f) {
+ case 0:
gen_op_srl();
opn = "srl";
- }
+ break;
+ case 1:
+ gen_op_rotr();
+ opn = "rotr";
+ break;
+ default:
+ MIPS_INVAL("invalid srl flag");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DSLL:
gen_op_dsll();
opn = "dsll";
opn = "dsra";
break;
case OPC_DSRL:
- if ((ctx->opcode >> 21) & 1) {
- gen_op_drotr();
- opn = "drotr";
- } else {
+ switch ((ctx->opcode >> 21) & 0x1f) {
+ case 0:
gen_op_dsrl();
opn = "dsrl";
- }
+ break;
+ case 1:
+ gen_op_drotr();
+ opn = "drotr";
+ break;
+ default:
+ MIPS_INVAL("invalid dsrl flag");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
break;
case OPC_DSLL32:
gen_op_dsll32();
opn = "dsra32";
break;
case OPC_DSRL32:
- if ((ctx->opcode >> 21) & 1) {
- gen_op_drotr32();
- opn = "drotr32";
- } else {
+ switch ((ctx->opcode >> 21) & 0x1f) {
+ case 0:
gen_op_dsrl32();
opn = "dsrl32";
- }
+ break;
+ case 1:
+ gen_op_drotr32();
+ opn = "drotr32";
+ break;
+ default:
+ MIPS_INVAL("invalid dsrl32 flag");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
break;
#endif
default:
gen_op_sub();
opn = "subu";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DADD:
save_cpu_state(ctx, 1);
gen_op_daddo();
opn = "srav";
break;
case OPC_SRLV:
- if ((ctx->opcode >> 6) & 1) {
- gen_op_rotrv();
- opn = "rotrv";
- } else {
+ switch ((ctx->opcode >> 6) & 0x1f) {
+ case 0:
gen_op_srlv();
opn = "srlv";
- }
+ break;
+ case 1:
+ gen_op_rotrv();
+ opn = "rotrv";
+ break;
+ default:
+ MIPS_INVAL("invalid srlv flag");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DSLLV:
gen_op_dsllv();
opn = "dsllv";
opn = "dsrav";
break;
case OPC_DSRLV:
- if ((ctx->opcode >> 6) & 1) {
- gen_op_drotrv();
- opn = "drotrv";
- } else {
+ switch ((ctx->opcode >> 6) & 0x1f) {
+ case 0:
gen_op_dsrlv();
opn = "dsrlv";
- }
+ break;
+ case 1:
+ gen_op_drotrv();
+ opn = "drotrv";
+ break;
+ default:
+ MIPS_INVAL("invalid dsrlv flag");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
break;
#endif
default:
gen_op_multu();
opn = "multu";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DDIV:
gen_op_ddiv();
opn = "ddiv";
gen_op_clz();
opn = "clz";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DCLO:
gen_op_dclo();
opn = "dclo";
static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
int rs, int rt, int32_t offset)
{
- target_ulong btarget;
- int blink, bcond;
+ target_ulong btarget = -1;
+ int blink = 0;
+ int bcond = 0;
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
+ fprintf(logfile,
+ "undefined branch in delay slot at PC " TARGET_FMT_lx "\n",
+ ctx->pc);
+ }
+ MIPS_INVAL("branch/jump in bdelay slot");
+ generate_exception(ctx, EXCP_RI);
+ return;
+ }
- btarget = -1;
- blink = 0;
- bcond = 0;
/* Load needed operands */
switch (opc) {
case OPC_BEQ:
/* Jump to register */
if (offset != 0 && offset != 16) {
/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
- others are reserved. */
+ others are reserved. */
generate_exception(ctx, EXCP_RI);
return;
}
case OPC_BLTZALL: /* 0 < 0 likely */
gen_op_set_T0(ctx->pc + 8);
gen_op_store_T0_gpr(31);
- gen_goto_tb(ctx, 0, ctx->pc + 4);
+ gen_goto_tb(ctx, 0, ctx->pc + 8);
return;
case OPC_BNEL: /* rx != rx likely */
case OPC_BGTZL: /* 0 > 0 likely */
case OPC_BLTZL: /* 0 < 0 likely */
/* Skip the instruction in the delay slot */
MIPS_DEBUG("bnever and skip");
- gen_goto_tb(ctx, 0, ctx->pc + 4);
+ gen_goto_tb(ctx, 0, ctx->pc + 8);
return;
case OPC_J:
ctx->hflags |= MIPS_HFLAG_B;
likely:
ctx->hflags |= MIPS_HFLAG_BL;
break;
+ default:
+ MIPS_INVAL("conditional branch/jump");
+ generate_exception(ctx, EXCP_RI);
+ return;
}
gen_op_set_bcond();
}
gen_op_set_T0(ctx->pc + 8);
gen_op_store_T0_gpr(blink);
}
- return;
}
/* special3 bitfield operations */
case 0:
switch (sel) {
case 0:
- gen_op_mfc0_index();
+ gen_op_mfc0_index();
rn = "Index";
break;
case 1:
-// gen_op_mfc0_mvpcontrol(); /* MT ASE */
+// gen_op_mfc0_mvpcontrol(); /* MT ASE */
rn = "MVPControl";
-// break;
+// break;
case 2:
-// gen_op_mfc0_mvpconf0(); /* MT ASE */
+// gen_op_mfc0_mvpconf0(); /* MT ASE */
rn = "MVPConf0";
-// break;
+// break;
case 3:
-// gen_op_mfc0_mvpconf1(); /* MT ASE */
+// gen_op_mfc0_mvpconf1(); /* MT ASE */
rn = "MVPConf1";
-// break;
+// break;
default:
goto die;
}
case 0:
gen_op_mfc0_random();
rn = "Random";
- break;
+ break;
case 1:
-// gen_op_mfc0_vpecontrol(); /* MT ASE */
+// gen_op_mfc0_vpecontrol(); /* MT ASE */
rn = "VPEControl";
-// break;
+// break;
case 2:
-// gen_op_mfc0_vpeconf0(); /* MT ASE */
+// gen_op_mfc0_vpeconf0(); /* MT ASE */
rn = "VPEConf0";
-// break;
+// break;
case 3:
-// gen_op_mfc0_vpeconf1(); /* MT ASE */
+// gen_op_mfc0_vpeconf1(); /* MT ASE */
rn = "VPEConf1";
-// break;
+// break;
case 4:
-// gen_op_mfc0_YQMask(); /* MT ASE */
+// gen_op_mfc0_YQMask(); /* MT ASE */
rn = "YQMask";
-// break;
+// break;
case 5:
-// gen_op_mfc0_vpeschedule(); /* MT ASE */
+// gen_op_mfc0_vpeschedule(); /* MT ASE */
rn = "VPESchedule";
-// break;
+// break;
case 6:
-// gen_op_mfc0_vpeschefback(); /* MT ASE */
+// gen_op_mfc0_vpeschefback(); /* MT ASE */
rn = "VPEScheFBack";
-// break;
+// break;
case 7:
-// gen_op_mfc0_vpeopt(); /* MT ASE */
+// gen_op_mfc0_vpeopt(); /* MT ASE */
rn = "VPEOpt";
-// break;
+// break;
default:
goto die;
}
case 2:
switch (sel) {
case 0:
- gen_op_mfc0_entrylo0();
- rn = "EntryLo0";
- break;
+ gen_op_mfc0_entrylo0();
+ rn = "EntryLo0";
+ break;
case 1:
-// gen_op_mfc0_tcstatus(); /* MT ASE */
- rn = "TCStatus";
-// break;
+// gen_op_mfc0_tcstatus(); /* MT ASE */
+ rn = "TCStatus";
+// break;
case 2:
-// gen_op_mfc0_tcbind(); /* MT ASE */
- rn = "TCBind";
-// break;
+// gen_op_mfc0_tcbind(); /* MT ASE */
+ rn = "TCBind";
+// break;
case 3:
-// gen_op_mfc0_tcrestart(); /* MT ASE */
- rn = "TCRestart";
-// break;
+// gen_op_mfc0_tcrestart(); /* MT ASE */
+ rn = "TCRestart";
+// break;
case 4:
-// gen_op_mfc0_tchalt(); /* MT ASE */
- rn = "TCHalt";
-// break;
+// gen_op_mfc0_tchalt(); /* MT ASE */
+ rn = "TCHalt";
+// break;
case 5:
-// gen_op_mfc0_tccontext(); /* MT ASE */
- rn = "TCContext";
-// break;
+// gen_op_mfc0_tccontext(); /* MT ASE */
+ rn = "TCContext";
+// break;
case 6:
-// gen_op_mfc0_tcschedule(); /* MT ASE */
- rn = "TCSchedule";
-// break;
+// gen_op_mfc0_tcschedule(); /* MT ASE */
+ rn = "TCSchedule";
+// break;
case 7:
-// gen_op_mfc0_tcschefback(); /* MT ASE */
- rn = "TCScheFBack";
-// break;
+// gen_op_mfc0_tcschefback(); /* MT ASE */
+ rn = "TCScheFBack";
+// break;
default:
goto die;
}
case 3:
switch (sel) {
case 0:
- gen_op_mfc0_entrylo1();
- rn = "EntryLo1";
- break;
+ gen_op_mfc0_entrylo1();
+ rn = "EntryLo1";
+ break;
default:
goto die;
- }
+ }
break;
case 4:
switch (sel) {
case 0:
- gen_op_mfc0_context();
- rn = "Context";
- break;
+ gen_op_mfc0_context();
+ rn = "Context";
+ break;
case 1:
-// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
- rn = "ContextConfig";
-// break;
+// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
+ rn = "ContextConfig";
+// break;
default:
goto die;
- }
+ }
break;
case 5:
switch (sel) {
case 0:
- gen_op_mfc0_pagemask();
- rn = "PageMask";
- break;
+ gen_op_mfc0_pagemask();
+ rn = "PageMask";
+ break;
case 1:
- gen_op_mfc0_pagegrain();
- rn = "PageGrain";
- break;
+ gen_op_mfc0_pagegrain();
+ rn = "PageGrain";
+ break;
default:
goto die;
- }
+ }
break;
case 6:
switch (sel) {
case 0:
- gen_op_mfc0_wired();
- rn = "Wired";
- break;
+ gen_op_mfc0_wired();
+ rn = "Wired";
+ break;
case 1:
-// gen_op_mfc0_srsconf0(); /* shadow registers */
- rn = "SRSConf0";
-// break;
+// gen_op_mfc0_srsconf0(); /* shadow registers */
+ rn = "SRSConf0";
+// break;
case 2:
-// gen_op_mfc0_srsconf1(); /* shadow registers */
- rn = "SRSConf1";
-// break;
+// gen_op_mfc0_srsconf1(); /* shadow registers */
+ rn = "SRSConf1";
+// break;
case 3:
-// gen_op_mfc0_srsconf2(); /* shadow registers */
- rn = "SRSConf2";
-// break;
+// gen_op_mfc0_srsconf2(); /* shadow registers */
+ rn = "SRSConf2";
+// break;
case 4:
-// gen_op_mfc0_srsconf3(); /* shadow registers */
- rn = "SRSConf3";
-// break;
+// gen_op_mfc0_srsconf3(); /* shadow registers */
+ rn = "SRSConf3";
+// break;
case 5:
-// gen_op_mfc0_srsconf4(); /* shadow registers */
- rn = "SRSConf4";
-// break;
+// gen_op_mfc0_srsconf4(); /* shadow registers */
+ rn = "SRSConf4";
+// break;
default:
goto die;
- }
+ }
break;
case 7:
switch (sel) {
case 0:
- gen_op_mfc0_hwrena();
- rn = "HWREna";
- break;
+ gen_op_mfc0_hwrena();
+ rn = "HWREna";
+ break;
default:
goto die;
- }
+ }
break;
case 8:
switch (sel) {
case 0:
- gen_op_mfc0_badvaddr();
- rn = "BadVaddr";
- break;
+ gen_op_mfc0_badvaddr();
+ rn = "BadVaddr";
+ break;
default:
goto die;
}
case 9:
switch (sel) {
case 0:
- gen_op_mfc0_count();
- rn = "Count";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mfc0_count();
+ rn = "Count";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
+ }
break;
case 10:
switch (sel) {
case 0:
- gen_op_mfc0_entryhi();
- rn = "EntryHi";
- break;
+ gen_op_mfc0_entryhi();
+ rn = "EntryHi";
+ break;
default:
goto die;
- }
+ }
break;
case 11:
switch (sel) {
case 0:
- gen_op_mfc0_compare();
- rn = "Compare";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mfc0_compare();
+ rn = "Compare";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
+ }
break;
case 12:
switch (sel) {
case 0:
- gen_op_mfc0_status();
- rn = "Status";
- break;
+ gen_op_mfc0_status();
+ rn = "Status";
+ break;
case 1:
- gen_op_mfc0_intctl();
- rn = "IntCtl";
- break;
+ gen_op_mfc0_intctl();
+ rn = "IntCtl";
+ break;
case 2:
- gen_op_mfc0_srsctl();
- rn = "SRSCtl";
- break;
+ gen_op_mfc0_srsctl();
+ rn = "SRSCtl";
+ break;
case 3:
-// gen_op_mfc0_srsmap(); /* shadow registers */
- rn = "SRSMap";
-// break;
+// gen_op_mfc0_srsmap(); /* shadow registers */
+ rn = "SRSMap";
+// break;
default:
goto die;
}
case 13:
switch (sel) {
case 0:
- gen_op_mfc0_cause();
- rn = "Cause";
- break;
+ gen_op_mfc0_cause();
+ rn = "Cause";
+ break;
default:
goto die;
}
case 14:
switch (sel) {
case 0:
- gen_op_mfc0_epc();
- rn = "EPC";
- break;
+ gen_op_mfc0_epc();
+ rn = "EPC";
+ break;
default:
goto die;
- }
+ }
break;
case 15:
switch (sel) {
case 0:
- gen_op_mfc0_prid();
- rn = "PRid";
- break;
+ gen_op_mfc0_prid();
+ rn = "PRid";
+ break;
case 1:
- gen_op_mfc0_ebase();
- rn = "EBase";
- break;
+ gen_op_mfc0_ebase();
+ rn = "EBase";
+ break;
default:
goto die;
}
case 16:
switch (sel) {
case 0:
- gen_op_mfc0_config0();
+ gen_op_mfc0_config0();
rn = "Config";
break;
case 1:
- gen_op_mfc0_config1();
+ gen_op_mfc0_config1();
rn = "Config1";
break;
case 2:
- gen_op_mfc0_config2();
+ gen_op_mfc0_config2();
rn = "Config2";
break;
case 3:
- gen_op_mfc0_config3();
+ gen_op_mfc0_config3();
rn = "Config3";
break;
- /* 6,7 are implementation dependent */
+ /* 4,5 are reserved */
+ /* 6,7 are implementation dependent */
+ case 6:
+ gen_op_mfc0_config6();
+ rn = "Config6";
+ break;
+ case 7:
+ gen_op_mfc0_config7();
+ rn = "Config7";
+ break;
default:
goto die;
}
case 17:
switch (sel) {
case 0:
- gen_op_mfc0_lladdr();
- rn = "LLAddr";
- break;
+ gen_op_mfc0_lladdr();
+ rn = "LLAddr";
+ break;
default:
goto die;
}
case 18:
switch (sel) {
case 0:
- gen_op_mfc0_watchlo0();
- rn = "WatchLo";
- break;
+ gen_op_mfc0_watchlo0();
+ rn = "WatchLo";
+ break;
case 1:
-// gen_op_mfc0_watchlo1();
- rn = "WatchLo1";
-// break;
+// gen_op_mfc0_watchlo1();
+ rn = "WatchLo1";
+// break;
case 2:
-// gen_op_mfc0_watchlo2();
- rn = "WatchLo2";
-// break;
+// gen_op_mfc0_watchlo2();
+ rn = "WatchLo2";
+// break;
case 3:
-// gen_op_mfc0_watchlo3();
- rn = "WatchLo3";
-// break;
+// gen_op_mfc0_watchlo3();
+ rn = "WatchLo3";
+// break;
case 4:
-// gen_op_mfc0_watchlo4();
- rn = "WatchLo4";
-// break;
+// gen_op_mfc0_watchlo4();
+ rn = "WatchLo4";
+// break;
case 5:
-// gen_op_mfc0_watchlo5();
- rn = "WatchLo5";
-// break;
+// gen_op_mfc0_watchlo5();
+ rn = "WatchLo5";
+// break;
case 6:
-// gen_op_mfc0_watchlo6();
- rn = "WatchLo6";
-// break;
+// gen_op_mfc0_watchlo6();
+ rn = "WatchLo6";
+// break;
case 7:
-// gen_op_mfc0_watchlo7();
- rn = "WatchLo7";
-// break;
+// gen_op_mfc0_watchlo7();
+ rn = "WatchLo7";
+// break;
default:
goto die;
}
case 19:
switch (sel) {
case 0:
- gen_op_mfc0_watchhi0();
- rn = "WatchHi";
- break;
+ gen_op_mfc0_watchhi0();
+ rn = "WatchHi";
+ break;
case 1:
-// gen_op_mfc0_watchhi1();
- rn = "WatchHi1";
-// break;
+// gen_op_mfc0_watchhi1();
+ rn = "WatchHi1";
+// break;
case 2:
-// gen_op_mfc0_watchhi2();
- rn = "WatchHi2";
-// break;
+// gen_op_mfc0_watchhi2();
+ rn = "WatchHi2";
+// break;
case 3:
-// gen_op_mfc0_watchhi3();
- rn = "WatchHi3";
-// break;
+// gen_op_mfc0_watchhi3();
+ rn = "WatchHi3";
+// break;
case 4:
-// gen_op_mfc0_watchhi4();
- rn = "WatchHi4";
-// break;
+// gen_op_mfc0_watchhi4();
+ rn = "WatchHi4";
+// break;
case 5:
-// gen_op_mfc0_watchhi5();
- rn = "WatchHi5";
-// break;
+// gen_op_mfc0_watchhi5();
+ rn = "WatchHi5";
+// break;
case 6:
-// gen_op_mfc0_watchhi6();
- rn = "WatchHi6";
-// break;
+// gen_op_mfc0_watchhi6();
+ rn = "WatchHi6";
+// break;
case 7:
-// gen_op_mfc0_watchhi7();
- rn = "WatchHi7";
-// break;
+// gen_op_mfc0_watchhi7();
+ rn = "WatchHi7";
+// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
- /* 64 bit MMU only */
- gen_op_mfc0_xcontext();
- rn = "XContext";
- break;
+ /* 64 bit MMU only */
+ gen_op_mfc0_xcontext();
+ rn = "XContext";
+ break;
default:
goto die;
}
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mfc0_framemask();
- rn = "Framemask";
- break;
+ gen_op_mfc0_framemask();
+ rn = "Framemask";
+ break;
default:
goto die;
}
break;
case 22:
- /* ignored */
- rn = "'Diagnostic"; /* implementation dependent */
- break;
+ /* ignored */
+ rn = "'Diagnostic"; /* implementation dependent */
+ break;
case 23:
switch (sel) {
case 0:
- gen_op_mfc0_debug(); /* EJTAG support */
- rn = "Debug";
- break;
+ gen_op_mfc0_debug(); /* EJTAG support */
+ rn = "Debug";
+ break;
case 1:
-// gen_op_mfc0_tracecontrol(); /* PDtrace support */
- rn = "TraceControl";
-// break;
+// gen_op_mfc0_tracecontrol(); /* PDtrace support */
+ rn = "TraceControl";
+// break;
case 2:
-// gen_op_mfc0_tracecontrol2(); /* PDtrace support */
- rn = "TraceControl2";
-// break;
+// gen_op_mfc0_tracecontrol2(); /* PDtrace support */
+ rn = "TraceControl2";
+// break;
case 3:
-// gen_op_mfc0_usertracedata(); /* PDtrace support */
- rn = "UserTraceData";
-// break;
+// gen_op_mfc0_usertracedata(); /* PDtrace support */
+ rn = "UserTraceData";
+// break;
case 4:
-// gen_op_mfc0_debug(); /* PDtrace support */
- rn = "TraceBPC";
-// break;
+// gen_op_mfc0_debug(); /* PDtrace support */
+ rn = "TraceBPC";
+// break;
default:
goto die;
}
case 24:
switch (sel) {
case 0:
- gen_op_mfc0_depc(); /* EJTAG support */
- rn = "DEPC";
- break;
+ gen_op_mfc0_depc(); /* EJTAG support */
+ rn = "DEPC";
+ break;
default:
goto die;
}
case 25:
switch (sel) {
case 0:
- gen_op_mfc0_performance0();
- rn = "Performance0";
+ gen_op_mfc0_performance0();
+ rn = "Performance0";
break;
case 1:
-// gen_op_mfc0_performance1();
- rn = "Performance1";
-// break;
+// gen_op_mfc0_performance1();
+ rn = "Performance1";
+// break;
case 2:
-// gen_op_mfc0_performance2();
- rn = "Performance2";
-// break;
+// gen_op_mfc0_performance2();
+ rn = "Performance2";
+// break;
case 3:
-// gen_op_mfc0_performance3();
- rn = "Performance3";
-// break;
+// gen_op_mfc0_performance3();
+ rn = "Performance3";
+// break;
case 4:
-// gen_op_mfc0_performance4();
- rn = "Performance4";
-// break;
+// gen_op_mfc0_performance4();
+ rn = "Performance4";
+// break;
case 5:
-// gen_op_mfc0_performance5();
- rn = "Performance5";
-// break;
+// gen_op_mfc0_performance5();
+ rn = "Performance5";
+// break;
case 6:
-// gen_op_mfc0_performance6();
- rn = "Performance6";
-// break;
+// gen_op_mfc0_performance6();
+ rn = "Performance6";
+// break;
case 7:
-// gen_op_mfc0_performance7();
- rn = "Performance7";
-// break;
+// gen_op_mfc0_performance7();
+ rn = "Performance7";
+// break;
default:
goto die;
}
switch (sel) {
/* ignored */
case 0 ... 3:
- rn = "CacheErr";
- break;
+ rn = "CacheErr";
+ break;
default:
goto die;
}
case 30:
switch (sel) {
case 0:
- gen_op_mfc0_errorepc();
- rn = "ErrorEPC";
- break;
+ gen_op_mfc0_errorepc();
+ rn = "ErrorEPC";
+ break;
default:
goto die;
}
case 31:
switch (sel) {
case 0:
- gen_op_mfc0_desave(); /* EJTAG support */
- rn = "DESAVE";
- break;
+ gen_op_mfc0_desave(); /* EJTAG support */
+ rn = "DESAVE";
+ break;
default:
goto die;
}
rn = "Index";
break;
case 1:
-// gen_op_mtc0_mvpcontrol(); /* MT ASE */
+// gen_op_mtc0_mvpcontrol(); /* MT ASE */
rn = "MVPControl";
-// break;
+// break;
case 2:
-// gen_op_mtc0_mvpconf0(); /* MT ASE */
+// gen_op_mtc0_mvpconf0(); /* MT ASE */
rn = "MVPConf0";
-// break;
+// break;
case 3:
-// gen_op_mtc0_mvpconf1(); /* MT ASE */
+// gen_op_mtc0_mvpconf1(); /* MT ASE */
rn = "MVPConf1";
-// break;
+// break;
default:
goto die;
}
case 1:
switch (sel) {
case 0:
- /* ignored */
+ /* ignored */
rn = "Random";
- break;
+ break;
case 1:
-// gen_op_mtc0_vpecontrol(); /* MT ASE */
+// gen_op_mtc0_vpecontrol(); /* MT ASE */
rn = "VPEControl";
-// break;
+// break;
case 2:
-// gen_op_mtc0_vpeconf0(); /* MT ASE */
+// gen_op_mtc0_vpeconf0(); /* MT ASE */
rn = "VPEConf0";
-// break;
+// break;
case 3:
-// gen_op_mtc0_vpeconf1(); /* MT ASE */
+// gen_op_mtc0_vpeconf1(); /* MT ASE */
rn = "VPEConf1";
-// break;
+// break;
case 4:
-// gen_op_mtc0_YQMask(); /* MT ASE */
+// gen_op_mtc0_YQMask(); /* MT ASE */
rn = "YQMask";
-// break;
+// break;
case 5:
-// gen_op_mtc0_vpeschedule(); /* MT ASE */
+// gen_op_mtc0_vpeschedule(); /* MT ASE */
rn = "VPESchedule";
-// break;
+// break;
case 6:
-// gen_op_mtc0_vpeschefback(); /* MT ASE */
+// gen_op_mtc0_vpeschefback(); /* MT ASE */
rn = "VPEScheFBack";
-// break;
+// break;
case 7:
-// gen_op_mtc0_vpeopt(); /* MT ASE */
+// gen_op_mtc0_vpeopt(); /* MT ASE */
rn = "VPEOpt";
-// break;
+// break;
default:
goto die;
}
case 2:
switch (sel) {
case 0:
- gen_op_mtc0_entrylo0();
- rn = "EntryLo0";
- break;
+ gen_op_mtc0_entrylo0();
+ rn = "EntryLo0";
+ break;
case 1:
-// gen_op_mtc0_tcstatus(); /* MT ASE */
- rn = "TCStatus";
-// break;
+// gen_op_mtc0_tcstatus(); /* MT ASE */
+ rn = "TCStatus";
+// break;
case 2:
-// gen_op_mtc0_tcbind(); /* MT ASE */
- rn = "TCBind";
-// break;
+// gen_op_mtc0_tcbind(); /* MT ASE */
+ rn = "TCBind";
+// break;
case 3:
-// gen_op_mtc0_tcrestart(); /* MT ASE */
- rn = "TCRestart";
-// break;
+// gen_op_mtc0_tcrestart(); /* MT ASE */
+ rn = "TCRestart";
+// break;
case 4:
-// gen_op_mtc0_tchalt(); /* MT ASE */
- rn = "TCHalt";
-// break;
+// gen_op_mtc0_tchalt(); /* MT ASE */
+ rn = "TCHalt";
+// break;
case 5:
-// gen_op_mtc0_tccontext(); /* MT ASE */
- rn = "TCContext";
-// break;
+// gen_op_mtc0_tccontext(); /* MT ASE */
+ rn = "TCContext";
+// break;
case 6:
-// gen_op_mtc0_tcschedule(); /* MT ASE */
- rn = "TCSchedule";
-// break;
+// gen_op_mtc0_tcschedule(); /* MT ASE */
+ rn = "TCSchedule";
+// break;
case 7:
-// gen_op_mtc0_tcschefback(); /* MT ASE */
- rn = "TCScheFBack";
-// break;
+// gen_op_mtc0_tcschefback(); /* MT ASE */
+ rn = "TCScheFBack";
+// break;
default:
goto die;
}
case 3:
switch (sel) {
case 0:
- gen_op_mtc0_entrylo1();
- rn = "EntryLo1";
- break;
+ gen_op_mtc0_entrylo1();
+ rn = "EntryLo1";
+ break;
default:
goto die;
- }
+ }
break;
case 4:
switch (sel) {
case 0:
- gen_op_mtc0_context();
- rn = "Context";
- break;
+ gen_op_mtc0_context();
+ rn = "Context";
+ break;
case 1:
-// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
- rn = "ContextConfig";
-// break;
+// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
+ rn = "ContextConfig";
+// break;
default:
goto die;
- }
+ }
break;
case 5:
switch (sel) {
case 0:
- gen_op_mtc0_pagemask();
- rn = "PageMask";
- break;
+ gen_op_mtc0_pagemask();
+ rn = "PageMask";
+ break;
case 1:
- gen_op_mtc0_pagegrain();
- rn = "PageGrain";
- break;
+ gen_op_mtc0_pagegrain();
+ rn = "PageGrain";
+ break;
default:
goto die;
- }
+ }
break;
case 6:
switch (sel) {
case 0:
- gen_op_mtc0_wired();
- rn = "Wired";
- break;
+ gen_op_mtc0_wired();
+ rn = "Wired";
+ break;
case 1:
-// gen_op_mtc0_srsconf0(); /* shadow registers */
- rn = "SRSConf0";
-// break;
+// gen_op_mtc0_srsconf0(); /* shadow registers */
+ rn = "SRSConf0";
+// break;
case 2:
-// gen_op_mtc0_srsconf1(); /* shadow registers */
- rn = "SRSConf1";
-// break;
+// gen_op_mtc0_srsconf1(); /* shadow registers */
+ rn = "SRSConf1";
+// break;
case 3:
-// gen_op_mtc0_srsconf2(); /* shadow registers */
- rn = "SRSConf2";
-// break;
+// gen_op_mtc0_srsconf2(); /* shadow registers */
+ rn = "SRSConf2";
+// break;
case 4:
-// gen_op_mtc0_srsconf3(); /* shadow registers */
- rn = "SRSConf3";
-// break;
+// gen_op_mtc0_srsconf3(); /* shadow registers */
+ rn = "SRSConf3";
+// break;
case 5:
-// gen_op_mtc0_srsconf4(); /* shadow registers */
- rn = "SRSConf4";
-// break;
+// gen_op_mtc0_srsconf4(); /* shadow registers */
+ rn = "SRSConf4";
+// break;
default:
goto die;
- }
+ }
break;
case 7:
switch (sel) {
case 0:
- gen_op_mtc0_hwrena();
- rn = "HWREna";
- break;
+ gen_op_mtc0_hwrena();
+ rn = "HWREna";
+ break;
default:
goto die;
- }
+ }
break;
case 8:
/* ignored */
case 9:
switch (sel) {
case 0:
- gen_op_mtc0_count();
- rn = "Count";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mtc0_count();
+ rn = "Count";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 10:
switch (sel) {
case 0:
- gen_op_mtc0_entryhi();
- rn = "EntryHi";
- break;
+ gen_op_mtc0_entryhi();
+ rn = "EntryHi";
+ break;
default:
goto die;
- }
+ }
break;
case 11:
switch (sel) {
case 0:
- gen_op_mtc0_compare();
- rn = "Compare";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mtc0_compare();
+ rn = "Compare";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 12:
switch (sel) {
case 0:
- gen_op_mtc0_status();
- rn = "Status";
- break;
+ gen_op_mtc0_status();
+ rn = "Status";
+ break;
case 1:
- gen_op_mtc0_intctl();
- rn = "IntCtl";
- break;
+ gen_op_mtc0_intctl();
+ rn = "IntCtl";
+ break;
case 2:
- gen_op_mtc0_srsctl();
- rn = "SRSCtl";
- break;
+ gen_op_mtc0_srsctl();
+ rn = "SRSCtl";
+ break;
case 3:
-// gen_op_mtc0_srsmap(); /* shadow registers */
- rn = "SRSMap";
-// break;
+// gen_op_mtc0_srsmap(); /* shadow registers */
+ rn = "SRSMap";
+// break;
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 13:
switch (sel) {
case 0:
- gen_op_mtc0_cause();
- rn = "Cause";
- break;
+ gen_op_mtc0_cause();
+ rn = "Cause";
+ break;
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 14:
switch (sel) {
case 0:
- gen_op_mtc0_epc();
- rn = "EPC";
- break;
+ gen_op_mtc0_epc();
+ rn = "EPC";
+ break;
default:
goto die;
- }
+ }
break;
case 15:
switch (sel) {
case 0:
- /* ignored */
- rn = "PRid";
- break;
+ /* ignored */
+ rn = "PRid";
+ break;
case 1:
- gen_op_mtc0_ebase();
- rn = "EBase";
- break;
+ gen_op_mtc0_ebase();
+ rn = "EBase";
+ break;
default:
goto die;
- }
+ }
break;
case 16:
switch (sel) {
case 0:
- gen_op_mtc0_config0();
+ gen_op_mtc0_config0();
rn = "Config";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 1:
- /* ignored */
+ /* ignored, read only */
rn = "Config1";
break;
case 2:
- gen_op_mtc0_config2();
+ gen_op_mtc0_config2();
rn = "Config2";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 3:
- /* ignored */
+ /* ignored, read only */
rn = "Config3";
break;
- /* 6,7 are implementation dependent */
+ /* 4,5 are reserved */
+ /* 6,7 are implementation dependent */
+ case 6:
+ /* ignored */
+ rn = "Config6";
+ break;
+ case 7:
+ /* ignored */
+ rn = "Config7";
+ break;
default:
rn = "Invalid config selector";
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 17:
switch (sel) {
case 0:
- /* ignored */
- rn = "LLAddr";
- break;
+ /* ignored */
+ rn = "LLAddr";
+ break;
default:
goto die;
}
case 18:
switch (sel) {
case 0:
- gen_op_mtc0_watchlo0();
- rn = "WatchLo";
- break;
+ gen_op_mtc0_watchlo0();
+ rn = "WatchLo";
+ break;
case 1:
-// gen_op_mtc0_watchlo1();
- rn = "WatchLo1";
-// break;
+// gen_op_mtc0_watchlo1();
+ rn = "WatchLo1";
+// break;
case 2:
-// gen_op_mtc0_watchlo2();
- rn = "WatchLo2";
-// break;
+// gen_op_mtc0_watchlo2();
+ rn = "WatchLo2";
+// break;
case 3:
-// gen_op_mtc0_watchlo3();
- rn = "WatchLo3";
-// break;
+// gen_op_mtc0_watchlo3();
+ rn = "WatchLo3";
+// break;
case 4:
-// gen_op_mtc0_watchlo4();
- rn = "WatchLo4";
-// break;
+// gen_op_mtc0_watchlo4();
+ rn = "WatchLo4";
+// break;
case 5:
-// gen_op_mtc0_watchlo5();
- rn = "WatchLo5";
-// break;
+// gen_op_mtc0_watchlo5();
+ rn = "WatchLo5";
+// break;
case 6:
-// gen_op_mtc0_watchlo6();
- rn = "WatchLo6";
-// break;
+// gen_op_mtc0_watchlo6();
+ rn = "WatchLo6";
+// break;
case 7:
-// gen_op_mtc0_watchlo7();
- rn = "WatchLo7";
-// break;
+// gen_op_mtc0_watchlo7();
+ rn = "WatchLo7";
+// break;
default:
goto die;
}
case 19:
switch (sel) {
case 0:
- gen_op_mtc0_watchhi0();
- rn = "WatchHi";
- break;
+ gen_op_mtc0_watchhi0();
+ rn = "WatchHi";
+ break;
case 1:
-// gen_op_mtc0_watchhi1();
- rn = "WatchHi1";
-// break;
+// gen_op_mtc0_watchhi1();
+ rn = "WatchHi1";
+// break;
case 2:
-// gen_op_mtc0_watchhi2();
- rn = "WatchHi2";
-// break;
+// gen_op_mtc0_watchhi2();
+ rn = "WatchHi2";
+// break;
case 3:
-// gen_op_mtc0_watchhi3();
- rn = "WatchHi3";
-// break;
+// gen_op_mtc0_watchhi3();
+ rn = "WatchHi3";
+// break;
case 4:
-// gen_op_mtc0_watchhi4();
- rn = "WatchHi4";
-// break;
+// gen_op_mtc0_watchhi4();
+ rn = "WatchHi4";
+// break;
case 5:
-// gen_op_mtc0_watchhi5();
- rn = "WatchHi5";
-// break;
+// gen_op_mtc0_watchhi5();
+ rn = "WatchHi5";
+// break;
case 6:
-// gen_op_mtc0_watchhi6();
- rn = "WatchHi6";
-// break;
+// gen_op_mtc0_watchhi6();
+ rn = "WatchHi6";
+// break;
case 7:
-// gen_op_mtc0_watchhi7();
- rn = "WatchHi7";
-// break;
+// gen_op_mtc0_watchhi7();
+ rn = "WatchHi7";
+// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
- /* 64 bit MMU only */
- gen_op_mtc0_xcontext();
- rn = "XContext";
- break;
+ /* 64 bit MMU only */
+ /* Nothing writable in lower 32 bits */
+ rn = "XContext";
+ break;
default:
goto die;
}
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mtc0_framemask();
- rn = "Framemask";
- break;
+ gen_op_mtc0_framemask();
+ rn = "Framemask";
+ break;
default:
goto die;
}
case 22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
- break;
+ break;
case 23:
switch (sel) {
case 0:
- gen_op_mtc0_debug(); /* EJTAG support */
- rn = "Debug";
- break;
+ gen_op_mtc0_debug(); /* EJTAG support */
+ rn = "Debug";
+ break;
case 1:
-// gen_op_mtc0_tracecontrol(); /* PDtrace support */
- rn = "TraceControl";
-// break;
+// gen_op_mtc0_tracecontrol(); /* PDtrace support */
+ rn = "TraceControl";
+// break;
case 2:
-// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
- rn = "TraceControl2";
-// break;
+// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
+ rn = "TraceControl2";
+// break;
case 3:
-// gen_op_mtc0_usertracedata(); /* PDtrace support */
- rn = "UserTraceData";
-// break;
+// gen_op_mtc0_usertracedata(); /* PDtrace support */
+ rn = "UserTraceData";
+// break;
case 4:
-// gen_op_mtc0_debug(); /* PDtrace support */
- rn = "TraceBPC";
-// break;
+// gen_op_mtc0_debug(); /* PDtrace support */
+ rn = "TraceBPC";
+// break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 24:
switch (sel) {
case 0:
- gen_op_mtc0_depc(); /* EJTAG support */
- rn = "DEPC";
- break;
+ gen_op_mtc0_depc(); /* EJTAG support */
+ rn = "DEPC";
+ break;
default:
goto die;
}
case 25:
switch (sel) {
case 0:
- gen_op_mtc0_performance0();
- rn = "Performance0";
- break;
+ gen_op_mtc0_performance0();
+ rn = "Performance0";
+ break;
case 1:
-// gen_op_mtc0_performance1();
- rn = "Performance1";
-// break;
+// gen_op_mtc0_performance1();
+ rn = "Performance1";
+// break;
case 2:
-// gen_op_mtc0_performance2();
- rn = "Performance2";
-// break;
+// gen_op_mtc0_performance2();
+ rn = "Performance2";
+// break;
case 3:
-// gen_op_mtc0_performance3();
- rn = "Performance3";
-// break;
+// gen_op_mtc0_performance3();
+ rn = "Performance3";
+// break;
case 4:
-// gen_op_mtc0_performance4();
- rn = "Performance4";
-// break;
+// gen_op_mtc0_performance4();
+ rn = "Performance4";
+// break;
case 5:
-// gen_op_mtc0_performance5();
- rn = "Performance5";
-// break;
+// gen_op_mtc0_performance5();
+ rn = "Performance5";
+// break;
case 6:
-// gen_op_mtc0_performance6();
- rn = "Performance6";
-// break;
+// gen_op_mtc0_performance6();
+ rn = "Performance6";
+// break;
case 7:
-// gen_op_mtc0_performance7();
- rn = "Performance7";
-// break;
+// gen_op_mtc0_performance7();
+ rn = "Performance7";
+// break;
default:
goto die;
}
break;
case 26:
- /* ignored */
+ /* ignored */
rn = "ECC";
- break;
+ break;
case 27:
switch (sel) {
case 0 ... 3:
- /* ignored */
- rn = "CacheErr";
- break;
+ /* ignored */
+ rn = "CacheErr";
+ break;
default:
goto die;
}
case 3:
case 5:
case 7:
- gen_op_mtc0_datalo();
+ gen_op_mtc0_datalo();
rn = "DataLo";
break;
default:
case 3:
case 5:
case 7:
- gen_op_mtc0_datahi();
+ gen_op_mtc0_datahi();
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- gen_op_mtc0_errorepc();
- rn = "ErrorEPC";
- break;
+ gen_op_mtc0_errorepc();
+ rn = "ErrorEPC";
+ break;
default:
goto die;
}
case 31:
switch (sel) {
case 0:
- gen_op_mtc0_desave(); /* EJTAG support */
- rn = "DESAVE";
- break;
+ gen_op_mtc0_desave(); /* EJTAG support */
+ rn = "DESAVE";
+ break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
default:
goto die;
generate_exception(ctx, EXCP_RI);
}
+#ifdef TARGET_MIPS64
static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
case 0:
switch (sel) {
case 0:
- gen_op_mfc0_index();
+ gen_op_mfc0_index();
rn = "Index";
break;
case 1:
-// gen_op_dmfc0_mvpcontrol(); /* MT ASE */
+// gen_op_dmfc0_mvpcontrol(); /* MT ASE */
rn = "MVPControl";
-// break;
+// break;
case 2:
-// gen_op_dmfc0_mvpconf0(); /* MT ASE */
+// gen_op_dmfc0_mvpconf0(); /* MT ASE */
rn = "MVPConf0";
-// break;
+// break;
case 3:
-// gen_op_dmfc0_mvpconf1(); /* MT ASE */
+// gen_op_dmfc0_mvpconf1(); /* MT ASE */
rn = "MVPConf1";
-// break;
+// break;
default:
goto die;
}
case 0:
gen_op_mfc0_random();
rn = "Random";
- break;
+ break;
case 1:
-// gen_op_dmfc0_vpecontrol(); /* MT ASE */
+// gen_op_dmfc0_vpecontrol(); /* MT ASE */
rn = "VPEControl";
-// break;
+// break;
case 2:
-// gen_op_dmfc0_vpeconf0(); /* MT ASE */
+// gen_op_dmfc0_vpeconf0(); /* MT ASE */
rn = "VPEConf0";
-// break;
+// break;
case 3:
-// gen_op_dmfc0_vpeconf1(); /* MT ASE */
+// gen_op_dmfc0_vpeconf1(); /* MT ASE */
rn = "VPEConf1";
-// break;
+// break;
case 4:
-// gen_op_dmfc0_YQMask(); /* MT ASE */
+// gen_op_dmfc0_YQMask(); /* MT ASE */
rn = "YQMask";
-// break;
+// break;
case 5:
-// gen_op_dmfc0_vpeschedule(); /* MT ASE */
+// gen_op_dmfc0_vpeschedule(); /* MT ASE */
rn = "VPESchedule";
-// break;
+// break;
case 6:
-// gen_op_dmfc0_vpeschefback(); /* MT ASE */
+// gen_op_dmfc0_vpeschefback(); /* MT ASE */
rn = "VPEScheFBack";
-// break;
+// break;
case 7:
-// gen_op_dmfc0_vpeopt(); /* MT ASE */
+// gen_op_dmfc0_vpeopt(); /* MT ASE */
rn = "VPEOpt";
-// break;
+// break;
default:
goto die;
}
case 2:
switch (sel) {
case 0:
- gen_op_dmfc0_entrylo0();
- rn = "EntryLo0";
- break;
+ gen_op_dmfc0_entrylo0();
+ rn = "EntryLo0";
+ break;
case 1:
-// gen_op_dmfc0_tcstatus(); /* MT ASE */
- rn = "TCStatus";
-// break;
+// gen_op_dmfc0_tcstatus(); /* MT ASE */
+ rn = "TCStatus";
+// break;
case 2:
-// gen_op_dmfc0_tcbind(); /* MT ASE */
- rn = "TCBind";
-// break;
+// gen_op_dmfc0_tcbind(); /* MT ASE */
+ rn = "TCBind";
+// break;
case 3:
-// gen_op_dmfc0_tcrestart(); /* MT ASE */
- rn = "TCRestart";
-// break;
+// gen_op_dmfc0_tcrestart(); /* MT ASE */
+ rn = "TCRestart";
+// break;
case 4:
-// gen_op_dmfc0_tchalt(); /* MT ASE */
- rn = "TCHalt";
-// break;
+// gen_op_dmfc0_tchalt(); /* MT ASE */
+ rn = "TCHalt";
+// break;
case 5:
-// gen_op_dmfc0_tccontext(); /* MT ASE */
- rn = "TCContext";
-// break;
+// gen_op_dmfc0_tccontext(); /* MT ASE */
+ rn = "TCContext";
+// break;
case 6:
-// gen_op_dmfc0_tcschedule(); /* MT ASE */
- rn = "TCSchedule";
-// break;
+// gen_op_dmfc0_tcschedule(); /* MT ASE */
+ rn = "TCSchedule";
+// break;
case 7:
-// gen_op_dmfc0_tcschefback(); /* MT ASE */
- rn = "TCScheFBack";
-// break;
+// gen_op_dmfc0_tcschefback(); /* MT ASE */
+ rn = "TCScheFBack";
+// break;
default:
goto die;
}
case 3:
switch (sel) {
case 0:
- gen_op_dmfc0_entrylo1();
- rn = "EntryLo1";
- break;
+ gen_op_dmfc0_entrylo1();
+ rn = "EntryLo1";
+ break;
default:
goto die;
- }
+ }
break;
case 4:
switch (sel) {
case 0:
- gen_op_dmfc0_context();
- rn = "Context";
- break;
+ gen_op_dmfc0_context();
+ rn = "Context";
+ break;
case 1:
-// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
- rn = "ContextConfig";
-// break;
+// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
+ rn = "ContextConfig";
+// break;
default:
goto die;
- }
+ }
break;
case 5:
switch (sel) {
case 0:
- gen_op_mfc0_pagemask();
- rn = "PageMask";
- break;
+ gen_op_mfc0_pagemask();
+ rn = "PageMask";
+ break;
case 1:
- gen_op_mfc0_pagegrain();
- rn = "PageGrain";
- break;
+ gen_op_mfc0_pagegrain();
+ rn = "PageGrain";
+ break;
default:
goto die;
- }
+ }
break;
case 6:
switch (sel) {
case 0:
- gen_op_mfc0_wired();
- rn = "Wired";
- break;
+ gen_op_mfc0_wired();
+ rn = "Wired";
+ break;
case 1:
-// gen_op_dmfc0_srsconf0(); /* shadow registers */
- rn = "SRSConf0";
-// break;
+// gen_op_dmfc0_srsconf0(); /* shadow registers */
+ rn = "SRSConf0";
+// break;
case 2:
-// gen_op_dmfc0_srsconf1(); /* shadow registers */
- rn = "SRSConf1";
-// break;
+// gen_op_dmfc0_srsconf1(); /* shadow registers */
+ rn = "SRSConf1";
+// break;
case 3:
-// gen_op_dmfc0_srsconf2(); /* shadow registers */
- rn = "SRSConf2";
-// break;
+// gen_op_dmfc0_srsconf2(); /* shadow registers */
+ rn = "SRSConf2";
+// break;
case 4:
-// gen_op_dmfc0_srsconf3(); /* shadow registers */
- rn = "SRSConf3";
-// break;
+// gen_op_dmfc0_srsconf3(); /* shadow registers */
+ rn = "SRSConf3";
+// break;
case 5:
-// gen_op_dmfc0_srsconf4(); /* shadow registers */
- rn = "SRSConf4";
-// break;
+// gen_op_dmfc0_srsconf4(); /* shadow registers */
+ rn = "SRSConf4";
+// break;
default:
goto die;
- }
+ }
break;
case 7:
switch (sel) {
case 0:
- gen_op_mfc0_hwrena();
- rn = "HWREna";
- break;
+ gen_op_mfc0_hwrena();
+ rn = "HWREna";
+ break;
default:
goto die;
- }
+ }
break;
case 8:
switch (sel) {
case 0:
- gen_op_dmfc0_badvaddr();
- rn = "BadVaddr";
- break;
+ gen_op_dmfc0_badvaddr();
+ rn = "BadVaddr";
+ break;
default:
goto die;
- }
+ }
break;
case 9:
switch (sel) {
case 0:
- gen_op_mfc0_count();
- rn = "Count";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mfc0_count();
+ rn = "Count";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
+ }
break;
case 10:
switch (sel) {
case 0:
- gen_op_dmfc0_entryhi();
- rn = "EntryHi";
- break;
+ gen_op_dmfc0_entryhi();
+ rn = "EntryHi";
+ break;
default:
goto die;
- }
+ }
break;
case 11:
switch (sel) {
case 0:
- gen_op_mfc0_compare();
- rn = "Compare";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mfc0_compare();
+ rn = "Compare";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
+ }
break;
case 12:
switch (sel) {
case 0:
- gen_op_mfc0_status();
- rn = "Status";
- break;
+ gen_op_mfc0_status();
+ rn = "Status";
+ break;
case 1:
- gen_op_mfc0_intctl();
- rn = "IntCtl";
- break;
+ gen_op_mfc0_intctl();
+ rn = "IntCtl";
+ break;
case 2:
- gen_op_mfc0_srsctl();
- rn = "SRSCtl";
- break;
+ gen_op_mfc0_srsctl();
+ rn = "SRSCtl";
+ break;
case 3:
- gen_op_mfc0_srsmap(); /* shadow registers */
- rn = "SRSMap";
- break;
+ gen_op_mfc0_srsmap(); /* shadow registers */
+ rn = "SRSMap";
+ break;
default:
goto die;
- }
+ }
break;
case 13:
switch (sel) {
case 0:
- gen_op_mfc0_cause();
- rn = "Cause";
- break;
+ gen_op_mfc0_cause();
+ rn = "Cause";
+ break;
default:
goto die;
- }
+ }
break;
case 14:
switch (sel) {
case 0:
- gen_op_dmfc0_epc();
- rn = "EPC";
- break;
+ gen_op_dmfc0_epc();
+ rn = "EPC";
+ break;
default:
goto die;
- }
+ }
break;
case 15:
switch (sel) {
case 0:
- gen_op_mfc0_prid();
- rn = "PRid";
- break;
+ gen_op_mfc0_prid();
+ rn = "PRid";
+ break;
case 1:
- gen_op_mfc0_ebase();
- rn = "EBase";
- break;
+ gen_op_mfc0_ebase();
+ rn = "EBase";
+ break;
default:
goto die;
- }
+ }
break;
case 16:
switch (sel) {
case 0:
- gen_op_mfc0_config0();
+ gen_op_mfc0_config0();
rn = "Config";
break;
case 1:
- gen_op_mfc0_config1();
+ gen_op_mfc0_config1();
rn = "Config1";
break;
case 2:
- gen_op_mfc0_config2();
+ gen_op_mfc0_config2();
rn = "Config2";
break;
case 3:
- gen_op_mfc0_config3();
+ gen_op_mfc0_config3();
rn = "Config3";
break;
/* 6,7 are implementation dependent */
case 17:
switch (sel) {
case 0:
- gen_op_dmfc0_lladdr();
- rn = "LLAddr";
- break;
+ gen_op_dmfc0_lladdr();
+ rn = "LLAddr";
+ break;
default:
goto die;
}
case 18:
switch (sel) {
case 0:
- gen_op_dmfc0_watchlo0();
- rn = "WatchLo";
- break;
+ gen_op_dmfc0_watchlo0();
+ rn = "WatchLo";
+ break;
case 1:
-// gen_op_dmfc0_watchlo1();
- rn = "WatchLo1";
-// break;
+// gen_op_dmfc0_watchlo1();
+ rn = "WatchLo1";
+// break;
case 2:
-// gen_op_dmfc0_watchlo2();
- rn = "WatchLo2";
-// break;
+// gen_op_dmfc0_watchlo2();
+ rn = "WatchLo2";
+// break;
case 3:
-// gen_op_dmfc0_watchlo3();
- rn = "WatchLo3";
-// break;
+// gen_op_dmfc0_watchlo3();
+ rn = "WatchLo3";
+// break;
case 4:
-// gen_op_dmfc0_watchlo4();
- rn = "WatchLo4";
-// break;
+// gen_op_dmfc0_watchlo4();
+ rn = "WatchLo4";
+// break;
case 5:
-// gen_op_dmfc0_watchlo5();
- rn = "WatchLo5";
-// break;
+// gen_op_dmfc0_watchlo5();
+ rn = "WatchLo5";
+// break;
case 6:
-// gen_op_dmfc0_watchlo6();
- rn = "WatchLo6";
-// break;
+// gen_op_dmfc0_watchlo6();
+ rn = "WatchLo6";
+// break;
case 7:
-// gen_op_dmfc0_watchlo7();
- rn = "WatchLo7";
-// break;
+// gen_op_dmfc0_watchlo7();
+ rn = "WatchLo7";
+// break;
default:
goto die;
}
case 19:
switch (sel) {
case 0:
- gen_op_mfc0_watchhi0();
- rn = "WatchHi";
- break;
+ gen_op_mfc0_watchhi0();
+ rn = "WatchHi";
+ break;
case 1:
-// gen_op_mfc0_watchhi1();
- rn = "WatchHi1";
-// break;
+// gen_op_mfc0_watchhi1();
+ rn = "WatchHi1";
+// break;
case 2:
-// gen_op_mfc0_watchhi2();
- rn = "WatchHi2";
-// break;
+// gen_op_mfc0_watchhi2();
+ rn = "WatchHi2";
+// break;
case 3:
-// gen_op_mfc0_watchhi3();
- rn = "WatchHi3";
-// break;
+// gen_op_mfc0_watchhi3();
+ rn = "WatchHi3";
+// break;
case 4:
-// gen_op_mfc0_watchhi4();
- rn = "WatchHi4";
-// break;
+// gen_op_mfc0_watchhi4();
+ rn = "WatchHi4";
+// break;
case 5:
-// gen_op_mfc0_watchhi5();
- rn = "WatchHi5";
-// break;
+// gen_op_mfc0_watchhi5();
+ rn = "WatchHi5";
+// break;
case 6:
-// gen_op_mfc0_watchhi6();
- rn = "WatchHi6";
-// break;
+// gen_op_mfc0_watchhi6();
+ rn = "WatchHi6";
+// break;
case 7:
-// gen_op_mfc0_watchhi7();
- rn = "WatchHi7";
-// break;
+// gen_op_mfc0_watchhi7();
+ rn = "WatchHi7";
+// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
- /* 64 bit MMU only */
- gen_op_dmfc0_xcontext();
- rn = "XContext";
- break;
+ /* 64 bit MMU only */
+ gen_op_dmfc0_xcontext();
+ rn = "XContext";
+ break;
default:
goto die;
}
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mfc0_framemask();
- rn = "Framemask";
- break;
+ gen_op_mfc0_framemask();
+ rn = "Framemask";
+ break;
default:
goto die;
}
break;
case 22:
- /* ignored */
- rn = "'Diagnostic"; /* implementation dependent */
- break;
+ /* ignored */
+ rn = "'Diagnostic"; /* implementation dependent */
+ break;
case 23:
switch (sel) {
case 0:
- gen_op_mfc0_debug(); /* EJTAG support */
- rn = "Debug";
- break;
+ gen_op_mfc0_debug(); /* EJTAG support */
+ rn = "Debug";
+ break;
case 1:
-// gen_op_dmfc0_tracecontrol(); /* PDtrace support */
- rn = "TraceControl";
-// break;
+// gen_op_dmfc0_tracecontrol(); /* PDtrace support */
+ rn = "TraceControl";
+// break;
case 2:
-// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
- rn = "TraceControl2";
-// break;
+// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
+ rn = "TraceControl2";
+// break;
case 3:
-// gen_op_dmfc0_usertracedata(); /* PDtrace support */
- rn = "UserTraceData";
-// break;
+// gen_op_dmfc0_usertracedata(); /* PDtrace support */
+ rn = "UserTraceData";
+// break;
case 4:
-// gen_op_dmfc0_debug(); /* PDtrace support */
- rn = "TraceBPC";
-// break;
+// gen_op_dmfc0_debug(); /* PDtrace support */
+ rn = "TraceBPC";
+// break;
default:
goto die;
}
case 24:
switch (sel) {
case 0:
- gen_op_dmfc0_depc(); /* EJTAG support */
- rn = "DEPC";
- break;
+ gen_op_dmfc0_depc(); /* EJTAG support */
+ rn = "DEPC";
+ break;
default:
goto die;
}
case 25:
switch (sel) {
case 0:
- gen_op_mfc0_performance0();
- rn = "Performance0";
+ gen_op_mfc0_performance0();
+ rn = "Performance0";
break;
case 1:
-// gen_op_dmfc0_performance1();
- rn = "Performance1";
-// break;
+// gen_op_dmfc0_performance1();
+ rn = "Performance1";
+// break;
case 2:
-// gen_op_dmfc0_performance2();
- rn = "Performance2";
-// break;
+// gen_op_dmfc0_performance2();
+ rn = "Performance2";
+// break;
case 3:
-// gen_op_dmfc0_performance3();
- rn = "Performance3";
-// break;
+// gen_op_dmfc0_performance3();
+ rn = "Performance3";
+// break;
case 4:
-// gen_op_dmfc0_performance4();
- rn = "Performance4";
-// break;
+// gen_op_dmfc0_performance4();
+ rn = "Performance4";
+// break;
case 5:
-// gen_op_dmfc0_performance5();
- rn = "Performance5";
-// break;
+// gen_op_dmfc0_performance5();
+ rn = "Performance5";
+// break;
case 6:
-// gen_op_dmfc0_performance6();
- rn = "Performance6";
-// break;
+// gen_op_dmfc0_performance6();
+ rn = "Performance6";
+// break;
case 7:
-// gen_op_dmfc0_performance7();
- rn = "Performance7";
-// break;
+// gen_op_dmfc0_performance7();
+ rn = "Performance7";
+// break;
default:
goto die;
}
switch (sel) {
/* ignored */
case 0 ... 3:
- rn = "CacheErr";
- break;
+ rn = "CacheErr";
+ break;
default:
goto die;
}
case 30:
switch (sel) {
case 0:
- gen_op_dmfc0_errorepc();
- rn = "ErrorEPC";
- break;
+ gen_op_dmfc0_errorepc();
+ rn = "ErrorEPC";
+ break;
default:
goto die;
}
case 31:
switch (sel) {
case 0:
- gen_op_mfc0_desave(); /* EJTAG support */
- rn = "DESAVE";
- break;
+ gen_op_mfc0_desave(); /* EJTAG support */
+ rn = "DESAVE";
+ break;
default:
goto die;
}
break;
default:
- goto die;
+ goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
rn = "Index";
break;
case 1:
-// gen_op_dmtc0_mvpcontrol(); /* MT ASE */
+// gen_op_dmtc0_mvpcontrol(); /* MT ASE */
rn = "MVPControl";
-// break;
+// break;
case 2:
-// gen_op_dmtc0_mvpconf0(); /* MT ASE */
+// gen_op_dmtc0_mvpconf0(); /* MT ASE */
rn = "MVPConf0";
-// break;
+// break;
case 3:
-// gen_op_dmtc0_mvpconf1(); /* MT ASE */
+// gen_op_dmtc0_mvpconf1(); /* MT ASE */
rn = "MVPConf1";
-// break;
+// break;
default:
goto die;
}
case 1:
switch (sel) {
case 0:
- /* ignored */
+ /* ignored */
rn = "Random";
- break;
+ break;
case 1:
-// gen_op_dmtc0_vpecontrol(); /* MT ASE */
+// gen_op_dmtc0_vpecontrol(); /* MT ASE */
rn = "VPEControl";
-// break;
+// break;
case 2:
-// gen_op_dmtc0_vpeconf0(); /* MT ASE */
+// gen_op_dmtc0_vpeconf0(); /* MT ASE */
rn = "VPEConf0";
-// break;
+// break;
case 3:
-// gen_op_dmtc0_vpeconf1(); /* MT ASE */
+// gen_op_dmtc0_vpeconf1(); /* MT ASE */
rn = "VPEConf1";
-// break;
+// break;
case 4:
-// gen_op_dmtc0_YQMask(); /* MT ASE */
+// gen_op_dmtc0_YQMask(); /* MT ASE */
rn = "YQMask";
-// break;
+// break;
case 5:
-// gen_op_dmtc0_vpeschedule(); /* MT ASE */
+// gen_op_dmtc0_vpeschedule(); /* MT ASE */
rn = "VPESchedule";
-// break;
+// break;
case 6:
-// gen_op_dmtc0_vpeschefback(); /* MT ASE */
+// gen_op_dmtc0_vpeschefback(); /* MT ASE */
rn = "VPEScheFBack";
-// break;
+// break;
case 7:
-// gen_op_dmtc0_vpeopt(); /* MT ASE */
+// gen_op_dmtc0_vpeopt(); /* MT ASE */
rn = "VPEOpt";
-// break;
+// break;
default:
goto die;
}
case 2:
switch (sel) {
case 0:
- gen_op_dmtc0_entrylo0();
- rn = "EntryLo0";
- break;
+ gen_op_dmtc0_entrylo0();
+ rn = "EntryLo0";
+ break;
case 1:
-// gen_op_dmtc0_tcstatus(); /* MT ASE */
- rn = "TCStatus";
-// break;
+// gen_op_dmtc0_tcstatus(); /* MT ASE */
+ rn = "TCStatus";
+// break;
case 2:
-// gen_op_dmtc0_tcbind(); /* MT ASE */
- rn = "TCBind";
-// break;
+// gen_op_dmtc0_tcbind(); /* MT ASE */
+ rn = "TCBind";
+// break;
case 3:
-// gen_op_dmtc0_tcrestart(); /* MT ASE */
- rn = "TCRestart";
-// break;
+// gen_op_dmtc0_tcrestart(); /* MT ASE */
+ rn = "TCRestart";
+// break;
case 4:
-// gen_op_dmtc0_tchalt(); /* MT ASE */
- rn = "TCHalt";
-// break;
+// gen_op_dmtc0_tchalt(); /* MT ASE */
+ rn = "TCHalt";
+// break;
case 5:
-// gen_op_dmtc0_tccontext(); /* MT ASE */
- rn = "TCContext";
-// break;
+// gen_op_dmtc0_tccontext(); /* MT ASE */
+ rn = "TCContext";
+// break;
case 6:
-// gen_op_dmtc0_tcschedule(); /* MT ASE */
- rn = "TCSchedule";
-// break;
+// gen_op_dmtc0_tcschedule(); /* MT ASE */
+ rn = "TCSchedule";
+// break;
case 7:
-// gen_op_dmtc0_tcschefback(); /* MT ASE */
- rn = "TCScheFBack";
-// break;
+// gen_op_dmtc0_tcschefback(); /* MT ASE */
+ rn = "TCScheFBack";
+// break;
default:
goto die;
}
case 3:
switch (sel) {
case 0:
- gen_op_dmtc0_entrylo1();
- rn = "EntryLo1";
- break;
+ gen_op_dmtc0_entrylo1();
+ rn = "EntryLo1";
+ break;
default:
goto die;
- }
+ }
break;
case 4:
switch (sel) {
case 0:
- gen_op_dmtc0_context();
- rn = "Context";
- break;
+ gen_op_dmtc0_context();
+ rn = "Context";
+ break;
case 1:
-// gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
- rn = "ContextConfig";
-// break;
+// gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
+ rn = "ContextConfig";
+// break;
default:
goto die;
- }
+ }
break;
case 5:
switch (sel) {
case 0:
- gen_op_mtc0_pagemask();
- rn = "PageMask";
- break;
+ gen_op_mtc0_pagemask();
+ rn = "PageMask";
+ break;
case 1:
- gen_op_mtc0_pagegrain();
- rn = "PageGrain";
- break;
+ gen_op_mtc0_pagegrain();
+ rn = "PageGrain";
+ break;
default:
goto die;
- }
+ }
break;
case 6:
switch (sel) {
case 0:
- gen_op_mtc0_wired();
- rn = "Wired";
- break;
+ gen_op_mtc0_wired();
+ rn = "Wired";
+ break;
case 1:
-// gen_op_dmtc0_srsconf0(); /* shadow registers */
- rn = "SRSConf0";
-// break;
+// gen_op_dmtc0_srsconf0(); /* shadow registers */
+ rn = "SRSConf0";
+// break;
case 2:
-// gen_op_dmtc0_srsconf1(); /* shadow registers */
- rn = "SRSConf1";
-// break;
+// gen_op_dmtc0_srsconf1(); /* shadow registers */
+ rn = "SRSConf1";
+// break;
case 3:
-// gen_op_dmtc0_srsconf2(); /* shadow registers */
- rn = "SRSConf2";
-// break;
+// gen_op_dmtc0_srsconf2(); /* shadow registers */
+ rn = "SRSConf2";
+// break;
case 4:
-// gen_op_dmtc0_srsconf3(); /* shadow registers */
- rn = "SRSConf3";
-// break;
+// gen_op_dmtc0_srsconf3(); /* shadow registers */
+ rn = "SRSConf3";
+// break;
case 5:
-// gen_op_dmtc0_srsconf4(); /* shadow registers */
- rn = "SRSConf4";
-// break;
+// gen_op_dmtc0_srsconf4(); /* shadow registers */
+ rn = "SRSConf4";
+// break;
default:
goto die;
- }
+ }
break;
case 7:
switch (sel) {
case 0:
- gen_op_mtc0_hwrena();
- rn = "HWREna";
- break;
+ gen_op_mtc0_hwrena();
+ rn = "HWREna";
+ break;
default:
goto die;
- }
+ }
break;
case 8:
/* ignored */
case 9:
switch (sel) {
case 0:
- gen_op_mtc0_count();
- rn = "Count";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mtc0_count();
+ rn = "Count";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 10:
switch (sel) {
case 0:
- gen_op_mtc0_entryhi();
- rn = "EntryHi";
- break;
+ gen_op_mtc0_entryhi();
+ rn = "EntryHi";
+ break;
default:
goto die;
- }
+ }
break;
case 11:
switch (sel) {
case 0:
- gen_op_mtc0_compare();
- rn = "Compare";
- break;
- /* 6,7 are implementation dependent */
+ gen_op_mtc0_compare();
+ rn = "Compare";
+ break;
+ /* 6,7 are implementation dependent */
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 12:
switch (sel) {
case 0:
- gen_op_mtc0_status();
- rn = "Status";
- break;
+ gen_op_mtc0_status();
+ rn = "Status";
+ break;
case 1:
- gen_op_mtc0_intctl();
- rn = "IntCtl";
- break;
+ gen_op_mtc0_intctl();
+ rn = "IntCtl";
+ break;
case 2:
- gen_op_mtc0_srsctl();
- rn = "SRSCtl";
- break;
+ gen_op_mtc0_srsctl();
+ rn = "SRSCtl";
+ break;
case 3:
- gen_op_mtc0_srsmap(); /* shadow registers */
- rn = "SRSMap";
- break;
+ gen_op_mtc0_srsmap(); /* shadow registers */
+ rn = "SRSMap";
+ break;
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 13:
switch (sel) {
case 0:
- gen_op_mtc0_cause();
- rn = "Cause";
- break;
+ gen_op_mtc0_cause();
+ rn = "Cause";
+ break;
default:
goto die;
- }
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 14:
switch (sel) {
case 0:
- gen_op_dmtc0_epc();
- rn = "EPC";
- break;
+ gen_op_dmtc0_epc();
+ rn = "EPC";
+ break;
default:
goto die;
- }
+ }
break;
case 15:
switch (sel) {
case 0:
- /* ignored */
- rn = "PRid";
- break;
+ /* ignored */
+ rn = "PRid";
+ break;
case 1:
- gen_op_mtc0_ebase();
- rn = "EBase";
- break;
+ gen_op_mtc0_ebase();
+ rn = "EBase";
+ break;
default:
goto die;
- }
+ }
break;
case 16:
switch (sel) {
case 0:
gen_op_mtc0_config0();
rn = "Config";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 1:
- /* ignored */
+ /* ignored */
rn = "Config1";
break;
case 2:
gen_op_mtc0_config2();
rn = "Config2";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 3:
- /* ignored */
+ /* ignored */
rn = "Config3";
break;
/* 6,7 are implementation dependent */
rn = "Invalid config selector";
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 17:
switch (sel) {
case 0:
- /* ignored */
- rn = "LLAddr";
- break;
+ /* ignored */
+ rn = "LLAddr";
+ break;
default:
goto die;
}
case 18:
switch (sel) {
case 0:
- gen_op_dmtc0_watchlo0();
- rn = "WatchLo";
- break;
+ gen_op_dmtc0_watchlo0();
+ rn = "WatchLo";
+ break;
case 1:
-// gen_op_dmtc0_watchlo1();
- rn = "WatchLo1";
-// break;
+// gen_op_dmtc0_watchlo1();
+ rn = "WatchLo1";
+// break;
case 2:
-// gen_op_dmtc0_watchlo2();
- rn = "WatchLo2";
-// break;
+// gen_op_dmtc0_watchlo2();
+ rn = "WatchLo2";
+// break;
case 3:
-// gen_op_dmtc0_watchlo3();
- rn = "WatchLo3";
-// break;
+// gen_op_dmtc0_watchlo3();
+ rn = "WatchLo3";
+// break;
case 4:
-// gen_op_dmtc0_watchlo4();
- rn = "WatchLo4";
-// break;
+// gen_op_dmtc0_watchlo4();
+ rn = "WatchLo4";
+// break;
case 5:
-// gen_op_dmtc0_watchlo5();
- rn = "WatchLo5";
-// break;
+// gen_op_dmtc0_watchlo5();
+ rn = "WatchLo5";
+// break;
case 6:
-// gen_op_dmtc0_watchlo6();
- rn = "WatchLo6";
-// break;
+// gen_op_dmtc0_watchlo6();
+ rn = "WatchLo6";
+// break;
case 7:
-// gen_op_dmtc0_watchlo7();
- rn = "WatchLo7";
-// break;
+// gen_op_dmtc0_watchlo7();
+ rn = "WatchLo7";
+// break;
default:
goto die;
}
case 19:
switch (sel) {
case 0:
- gen_op_mtc0_watchhi0();
- rn = "WatchHi";
- break;
+ gen_op_mtc0_watchhi0();
+ rn = "WatchHi";
+ break;
case 1:
-// gen_op_dmtc0_watchhi1();
- rn = "WatchHi1";
-// break;
+// gen_op_dmtc0_watchhi1();
+ rn = "WatchHi1";
+// break;
case 2:
-// gen_op_dmtc0_watchhi2();
- rn = "WatchHi2";
-// break;
+// gen_op_dmtc0_watchhi2();
+ rn = "WatchHi2";
+// break;
case 3:
-// gen_op_dmtc0_watchhi3();
- rn = "WatchHi3";
-// break;
+// gen_op_dmtc0_watchhi3();
+ rn = "WatchHi3";
+// break;
case 4:
-// gen_op_dmtc0_watchhi4();
- rn = "WatchHi4";
-// break;
+// gen_op_dmtc0_watchhi4();
+ rn = "WatchHi4";
+// break;
case 5:
-// gen_op_dmtc0_watchhi5();
- rn = "WatchHi5";
-// break;
+// gen_op_dmtc0_watchhi5();
+ rn = "WatchHi5";
+// break;
case 6:
-// gen_op_dmtc0_watchhi6();
- rn = "WatchHi6";
-// break;
+// gen_op_dmtc0_watchhi6();
+ rn = "WatchHi6";
+// break;
case 7:
-// gen_op_dmtc0_watchhi7();
- rn = "WatchHi7";
-// break;
+// gen_op_dmtc0_watchhi7();
+ rn = "WatchHi7";
+// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
- /* 64 bit MMU only */
- gen_op_dmtc0_xcontext();
- rn = "XContext";
- break;
+ /* 64 bit MMU only */
+ gen_op_dmtc0_xcontext();
+ rn = "XContext";
+ break;
default:
goto die;
}
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mtc0_framemask();
- rn = "Framemask";
- break;
+ gen_op_mtc0_framemask();
+ rn = "Framemask";
+ break;
default:
goto die;
}
case 22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
- break;
+ break;
case 23:
switch (sel) {
case 0:
- gen_op_mtc0_debug(); /* EJTAG support */
- rn = "Debug";
- break;
+ gen_op_mtc0_debug(); /* EJTAG support */
+ rn = "Debug";
+ break;
case 1:
-// gen_op_dmtc0_tracecontrol(); /* PDtrace support */
- rn = "TraceControl";
-// break;
+// gen_op_dmtc0_tracecontrol(); /* PDtrace support */
+ rn = "TraceControl";
+// break;
case 2:
-// gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
- rn = "TraceControl2";
-// break;
+// gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
+ rn = "TraceControl2";
+// break;
case 3:
-// gen_op_dmtc0_usertracedata(); /* PDtrace support */
- rn = "UserTraceData";
-// break;
+// gen_op_dmtc0_usertracedata(); /* PDtrace support */
+ rn = "UserTraceData";
+// break;
case 4:
-// gen_op_dmtc0_debug(); /* PDtrace support */
- rn = "TraceBPC";
-// break;
+// gen_op_dmtc0_debug(); /* PDtrace support */
+ rn = "TraceBPC";
+// break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
case 24:
switch (sel) {
case 0:
- gen_op_dmtc0_depc(); /* EJTAG support */
- rn = "DEPC";
- break;
+ gen_op_dmtc0_depc(); /* EJTAG support */
+ rn = "DEPC";
+ break;
default:
goto die;
}
case 25:
switch (sel) {
case 0:
- gen_op_mtc0_performance0();
- rn = "Performance0";
- break;
+ gen_op_mtc0_performance0();
+ rn = "Performance0";
+ break;
case 1:
-// gen_op_dmtc0_performance1();
- rn = "Performance1";
-// break;
+// gen_op_dmtc0_performance1();
+ rn = "Performance1";
+// break;
case 2:
-// gen_op_dmtc0_performance2();
- rn = "Performance2";
-// break;
+// gen_op_dmtc0_performance2();
+ rn = "Performance2";
+// break;
case 3:
-// gen_op_dmtc0_performance3();
- rn = "Performance3";
-// break;
+// gen_op_dmtc0_performance3();
+ rn = "Performance3";
+// break;
case 4:
-// gen_op_dmtc0_performance4();
- rn = "Performance4";
-// break;
+// gen_op_dmtc0_performance4();
+ rn = "Performance4";
+// break;
case 5:
-// gen_op_dmtc0_performance5();
- rn = "Performance5";
-// break;
+// gen_op_dmtc0_performance5();
+ rn = "Performance5";
+// break;
case 6:
-// gen_op_dmtc0_performance6();
- rn = "Performance6";
-// break;
+// gen_op_dmtc0_performance6();
+ rn = "Performance6";
+// break;
case 7:
-// gen_op_dmtc0_performance7();
- rn = "Performance7";
-// break;
+// gen_op_dmtc0_performance7();
+ rn = "Performance7";
+// break;
default:
goto die;
}
- break;
+ break;
case 26:
- /* ignored */
+ /* ignored */
rn = "ECC";
- break;
+ break;
case 27:
switch (sel) {
case 0 ... 3:
- /* ignored */
- rn = "CacheErr";
- break;
+ /* ignored */
+ rn = "CacheErr";
+ break;
default:
goto die;
}
- break;
+ break;
case 28:
switch (sel) {
case 0:
case 3:
case 5:
case 7:
- gen_op_mtc0_datalo();
+ gen_op_mtc0_datalo();
rn = "DataLo";
break;
default:
case 3:
case 5:
case 7:
- gen_op_mtc0_datahi();
+ gen_op_mtc0_datahi();
rn = "DataHi";
break;
default:
rn = "invalid sel";
goto die;
}
- break;
+ break;
case 30:
switch (sel) {
case 0:
- gen_op_dmtc0_errorepc();
- rn = "ErrorEPC";
- break;
+ gen_op_dmtc0_errorepc();
+ rn = "ErrorEPC";
+ break;
default:
goto die;
}
case 31:
switch (sel) {
case 0:
- gen_op_mtc0_desave(); /* EJTAG support */
- rn = "DESAVE";
- break;
+ gen_op_mtc0_desave(); /* EJTAG support */
+ rn = "DESAVE";
+ break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
break;
default:
- goto die;
+ goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
#endif
generate_exception(ctx, EXCP_RI);
}
+#endif /* TARGET_MIPS64 */
static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
{
const char *opn = "unk";
- if ((!ctx->CP0_Status & (1 << CP0St_CU0) &&
- (ctx->hflags & MIPS_HFLAG_UM)) &&
- !(ctx->hflags & MIPS_HFLAG_ERL) &&
- !(ctx->hflags & MIPS_HFLAG_EXL)) {
- if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile, "CP0 is not usable\n");
- }
- generate_exception (ctx, EXCP_CpU);
- return;
- }
-
switch (opc) {
case OPC_MFC0:
if (rt == 0) {
opn = "mfc0";
break;
case OPC_MTC0:
- /* If we get an exception, we want to restart at next instruction */
- /* XXX: breaks for mtc in delay slot */
- ctx->pc += 4;
- save_cpu_state(ctx, 1);
- ctx->pc -= 4;
GEN_LOAD_REG_TN(T0, rt);
gen_mtc0(ctx, rd, ctx->opcode & 0x7);
opn = "mtc0";
break;
+#ifdef TARGET_MIPS64
case OPC_DMFC0:
if (rt == 0) {
/* Treat as NOP */
opn = "dmfc0";
break;
case OPC_DMTC0:
- /* If we get an exception, we want to restart at next instruction */
- /* XXX: breaks for dmtc in delay slot */
- ctx->pc += 4;
- save_cpu_state(ctx, 1);
- ctx->pc -= 4;
GEN_LOAD_REG_TN(T0, rt);
gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
opn = "dmtc0";
break;
+#endif
#if defined(MIPS_USES_R4K_TLB)
case OPC_TLBWI:
gen_op_tlbwi();
MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
}
-#ifdef MIPS_USES_FPU
-
/* CP1 Branches (before delay slot) */
static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
int32_t offset)
break;
default:
MIPS_INVAL("cp1 branch/jump");
- generate_exception_err (ctx, EXCP_RI, 1);
+ generate_exception (ctx, EXCP_RI);
return;
}
gen_op_set_bcond();
case OPC_CFC1:
if (fs != 0 && fs != 31) {
MIPS_INVAL("cfc1 freg");
- generate_exception_err (ctx, EXCP_RI, 1);
+ generate_exception (ctx, EXCP_RI);
return;
}
GEN_LOAD_IMM_TN(T1, fs);
case OPC_CTC1:
if (fs != 0 && fs != 31) {
MIPS_INVAL("ctc1 freg");
- generate_exception_err (ctx, EXCP_RI, 1);
+ generate_exception (ctx, EXCP_RI);
return;
}
GEN_LOAD_IMM_TN(T1, fs);
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
((ctx->opcode >> 16) & 0x1F));
}
- generate_exception_err (ctx, EXCP_RI, 1);
+ generate_exception (ctx, EXCP_RI);
return;
}
MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
*/
#define CHECK_FR(ctx, freg) do { \
if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
- generate_exception_err (ctx, EXCP_RI, 1); \
+ generate_exception (ctx, EXCP_RI); \
return; \
} \
} while(0)
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
((ctx->opcode >> 16) & 0x1F));
}
- generate_exception_err (ctx, EXCP_RI, 1);
+ generate_exception (ctx, EXCP_RI);
return;
}
if (binary)
gen_op_movt(ccbit, rd, rs);
}
-#endif /* MIPS_USES_FPU */
-
/* ISA extensions (ASEs) */
/* MIPS16 extension to MIPS32 */
/* SmartMIPS extension to MIPS32 */
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* Coprocessor 3 (FPU) */
/* MDMX extension to MIPS64 */
gen_set_label(l1);
}
-static void decode_opc (DisasContext *ctx)
+static void decode_opc (CPUState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
/* make sure instructions are on a word boundary */
if (ctx->pc & 0x3) {
+ env->CP0_BadVAddr = ctx->pc;
generate_exception(ctx, EXCP_AdEL);
return;
}
case OPC_MTLO: /* Move to HI/LO */
gen_HILO(ctx, op1, rs);
break;
- case OPC_PMON: /* Pmon entry point */
+ case OPC_PMON: /* Pmon entry point, also R4010 selsl */
+#ifdef MIPS_STRICT_STANDARD
+ MIPS_INVAL("PMON / selsl");
+ generate_exception(ctx, EXCP_RI);
+#else
gen_op_pmon(sa);
+#endif
break;
case OPC_SYSCALL:
generate_exception(ctx, EXCP_SYSCALL);
- ctx->bstate = BS_EXCP;
break;
case OPC_BREAK:
generate_exception(ctx, EXCP_BREAK);
break;
- case OPC_SPIM: /* SPIM ? */
+ case OPC_SPIM:
+#ifdef MIPS_STRICT_STANDARD
+ MIPS_INVAL("SPIM");
+ generate_exception(ctx, EXCP_RI);
+#else
/* Implemented as RI exception for now. */
MIPS_INVAL("spim (unofficial)");
generate_exception(ctx, EXCP_RI);
+#endif
break;
case OPC_SYNC:
/* Treat as a noop. */
break;
-#ifdef MIPS_USES_FPU
case OPC_MOVCI:
- gen_op_cp1_enabled();
- gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
- (ctx->opcode >> 16) & 1);
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ save_cpu_state(ctx, 1);
+ gen_op_cp1_enabled();
+ gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
+ (ctx->opcode >> 16) & 1);
+ } else {
+ generate_exception_err(ctx, EXCP_CpU, 1);
+ }
break;
-#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
}
/* Treat as a noop */
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DCLZ ... OPC_DCLO:
gen_cl(ctx, op1, rd, rs);
break;
}
break;
case OPC_SPECIAL3:
- op1 = MASK_SPECIAL3(ctx->opcode);
- switch (op1) {
- case OPC_EXT:
- case OPC_INS:
+ op1 = MASK_SPECIAL3(ctx->opcode);
+ switch (op1) {
+ case OPC_EXT:
+ case OPC_INS:
+ gen_bitops(ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_BSHFL:
+ op2 = MASK_BSHFL(ctx->opcode);
+ switch (op2) {
+ case OPC_WSBH:
+ GEN_LOAD_REG_TN(T1, rt);
+ gen_op_wsbh();
+ break;
+ case OPC_SEB:
+ GEN_LOAD_REG_TN(T1, rt);
+ gen_op_seb();
+ break;
+ case OPC_SEH:
+ GEN_LOAD_REG_TN(T1, rt);
+ gen_op_seh();
+ break;
+ default: /* Invalid */
+ MIPS_INVAL("bshfl");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+ GEN_STORE_TN_REG(rd, T0);
+ break;
+ case OPC_RDHWR:
+ switch (rd) {
+ case 0:
+ save_cpu_state(ctx, 1);
+ gen_op_rdhwr_cpunum();
+ break;
+ case 1:
+ save_cpu_state(ctx, 1);
+ gen_op_rdhwr_synci_step();
+ break;
+ case 2:
+ save_cpu_state(ctx, 1);
+ gen_op_rdhwr_cc();
+ break;
+ case 3:
+ save_cpu_state(ctx, 1);
+ gen_op_rdhwr_ccres();
+ break;
+ case 29:
+#if defined (CONFIG_USER_ONLY)
+ gen_op_tls_value ();
+ break;
+#endif
+ default: /* Invalid */
+ MIPS_INVAL("rdhwr");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+ GEN_STORE_TN_REG(rt, T0);
+ break;
+#ifdef TARGET_MIPS64
+ case OPC_DEXTM ... OPC_DEXT:
+ case OPC_DINSM ... OPC_DINS:
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
- case OPC_BSHFL:
- op2 = MASK_BSHFL(ctx->opcode);
+ case OPC_DBSHFL:
+ op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
- case OPC_WSBH:
+ case OPC_DSBH:
GEN_LOAD_REG_TN(T1, rt);
- gen_op_wsbh();
+ gen_op_dsbh();
break;
- case OPC_SEB:
+ case OPC_DSHD:
GEN_LOAD_REG_TN(T1, rt);
- gen_op_seb();
- break;
- case OPC_SEH:
- GEN_LOAD_REG_TN(T1, rt);
- gen_op_seh();
- break;
- default: /* Invalid */
- MIPS_INVAL("bshfl");
- generate_exception(ctx, EXCP_RI);
+ gen_op_dshd();
break;
- }
- GEN_STORE_TN_REG(rd, T0);
- break;
- case OPC_RDHWR:
- switch (rd) {
- case 0:
- gen_op_rdhwr_cpunum();
- break;
- case 1:
- gen_op_rdhwr_synci_step();
- break;
- case 2:
- gen_op_rdhwr_cc();
- break;
- case 3:
- gen_op_rdhwr_ccres();
- break;
- default: /* Invalid */
- MIPS_INVAL("rdhwr");
- generate_exception(ctx, EXCP_RI);
- break;
- }
- GEN_STORE_TN_REG(rt, T0);
- break;
-#ifdef MIPS_HAS_MIPS64
- case OPC_DEXTM ... OPC_DEXT:
- case OPC_DINSM ... OPC_DINS:
- gen_bitops(ctx, op1, rt, rs, sa, rd);
- break;
- case OPC_DBSHFL:
- op2 = MASK_DBSHFL(ctx->opcode);
- switch (op2) {
- case OPC_DSBH:
- GEN_LOAD_REG_TN(T1, rt);
- gen_op_dsbh();
- break;
- case OPC_DSHD:
- GEN_LOAD_REG_TN(T1, rt);
- gen_op_dshd();
- break;
default: /* Invalid */
MIPS_INVAL("dbshfl");
generate_exception(ctx, EXCP_RI);
break;
- }
- GEN_STORE_TN_REG(rd, T0);
+ }
+ GEN_STORE_TN_REG(rd, T0);
#endif
default: /* Invalid */
MIPS_INVAL("special3");
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SYNCI:
- /* treat as noop */
+ /* treat as noop */
break;
default: /* Invalid */
MIPS_INVAL("REGIMM");
}
break;
case OPC_CP0:
+ save_cpu_state(ctx, 1);
+ gen_op_cp0_enabled();
op1 = MASK_CP0(ctx->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DMFC0:
case OPC_DMTC0:
#endif
}
GEN_STORE_TN_REG(rt, T0);
break;
- /* Shadow registers (not implemented). */
case OPC_RDPGPR:
case OPC_WRPGPR:
+ if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) {
+ /* Shadow registers not implemented. */
+ GEN_LOAD_REG_TN(T0, rt);
+ GEN_STORE_TN_REG(rd, T0);
+ } else
+ generate_exception(ctx, EXCP_RI);
+ break;
default:
generate_exception(ctx, EXCP_RI);
break;
case OPC_LDC1:
case OPC_SWC1:
case OPC_SDC1:
-#if defined(MIPS_USES_FPU)
- save_cpu_state(ctx, 1);
- gen_op_cp1_enabled();
- gen_flt_ldst(ctx, op, rt, rs, imm);
-#else
- generate_exception_err(ctx, EXCP_CpU, 1);
-#endif
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ save_cpu_state(ctx, 1);
+ gen_op_cp1_enabled();
+ gen_flt_ldst(ctx, op, rt, rs, imm);
+ } else {
+ generate_exception_err(ctx, EXCP_CpU, 1);
+ }
break;
case OPC_CP1:
-#if defined(MIPS_USES_FPU)
- save_cpu_state(ctx, 1);
- gen_op_cp1_enabled();
- op1 = MASK_CP1(ctx->opcode);
- switch (op1) {
- case OPC_MFC1:
- case OPC_CFC1:
- case OPC_MTC1:
- case OPC_CTC1:
-#ifdef MIPS_HAS_MIPS64
- case OPC_DMFC1:
- case OPC_DMTC1:
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ save_cpu_state(ctx, 1);
+ gen_op_cp1_enabled();
+ op1 = MASK_CP1(ctx->opcode);
+ switch (op1) {
+ case OPC_MFC1:
+ case OPC_CFC1:
+ case OPC_MTC1:
+ case OPC_CTC1:
+#ifdef TARGET_MIPS64
+ case OPC_DMFC1:
+ case OPC_DMTC1:
#endif
- gen_cp1(ctx, op1, rt, rd);
- break;
- case OPC_BC1:
- gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
- return;
- case OPC_S_FMT:
- case OPC_D_FMT:
- case OPC_W_FMT:
- case OPC_L_FMT:
- gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
- break;
- default:
- generate_exception_err(ctx, EXCP_RI, 1);
- break;
+ gen_cp1(ctx, op1, rt, rd);
+ break;
+ case OPC_BC1:
+ gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
+ return;
+ case OPC_S_FMT:
+ case OPC_D_FMT:
+ case OPC_W_FMT:
+ case OPC_L_FMT:
+ gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
+ break;
+ default:
+ generate_exception (ctx, EXCP_RI);
+ break;
+ }
+ } else {
+ generate_exception_err(ctx, EXCP_CpU, 1);
}
-#else
- generate_exception_err(ctx, EXCP_CpU, 1);
-#endif
break;
/* COP2. */
generate_exception_err(ctx, EXCP_CpU, 2);
break;
-#ifdef MIPS_USES_FPU
case OPC_CP3:
- gen_op_cp1_enabled();
- op1 = MASK_CP3(ctx->opcode);
- switch (op1) {
- /* Not implemented */
- default:
- generate_exception_err(ctx, EXCP_RI, 1);
- break;
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ save_cpu_state(ctx, 1);
+ gen_op_cp1_enabled();
+ op1 = MASK_CP3(ctx->opcode);
+ switch (op1) {
+ case OPC_PREFX:
+ /* treat as noop */
+ break;
+ /* Not implemented */
+ default:
+ generate_exception (ctx, EXCP_RI);
+ break;
+ }
+ } else {
+ generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
-#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* MIPS64 opcodes */
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
break;
}
if (ctx->hflags & MIPS_HFLAG_BMASK) {
- int hflags = ctx->hflags;
+ int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
/* Branches completion */
ctx->hflags &= ~MIPS_HFLAG_BMASK;
ctx->bstate = BS_BRANCH;
}
}
-int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
- int search_pc)
+static inline int
+gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
+ int search_pc)
{
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
gen_opc_instr_start[lj] = 1;
}
ctx.opcode = ldl_code(ctx.pc);
- decode_opc(&ctx);
+ decode_opc(env, &ctx);
ctx.pc += 4;
if (env->singlestep_enabled)
if (env->singlestep_enabled) {
save_cpu_state(ctxp, ctx.bstate == BS_NONE);
gen_op_debug();
- goto done_generating;
- }
- else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
- save_cpu_state(ctxp, 0);
- gen_goto_tb(&ctx, 0, ctx.pc);
+ } else {
+ switch (ctx.bstate) {
+ case BS_EXCP:
+ gen_op_interrupt_restart();
+ break;
+ case BS_STOP:
+ gen_op_interrupt_restart();
+ /* Fall through. */
+ case BS_NONE:
+ save_cpu_state(ctxp, 0);
+ gen_goto_tb(&ctx, 0, ctx.pc);
+ break;
+ case BS_BRANCH:
+ default:
+ break;
+ }
+ gen_op_reset_T0();
+ /* Generate the return instruction. */
+ gen_op_exit_tb();
}
- gen_op_reset_T0();
- /* Generate the return instruction */
- gen_op_exit_tb();
done_generating:
*gen_opc_ptr = INDEX_op_end;
if (search_pc) {
return gen_intermediate_code_internal(env, tb, 1);
}
-#ifdef MIPS_USES_FPU
-
void fpu_dump_state(CPUState *env, FILE *f,
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
}
}
-#endif /* MIPS_USES_FPU */
-
-#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
/* Debug help: The architecture requires 32bit code to maintain proper
sign-extened values on 64bit machines. */
}
c0_status = env->CP0_Status;
- if (env->hflags & MIPS_HFLAG_UM)
- c0_status |= (1 << CP0St_UM);
- if (env->hflags & MIPS_HFLAG_ERL)
- c0_status |= (1 << CP0St_ERL);
- if (env->hflags & MIPS_HFLAG_EXL)
- c0_status |= (1 << CP0St_EXL);
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
c0_status, env->CP0_Cause, env->CP0_EPC);
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
-#ifdef MIPS_USES_FPU
if (c0_status & (1 << CP0St_CU1))
fpu_dump_state(env, f, cpu_fprintf, flags);
-#endif
-#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
#endif
}
} else {
env->CP0_ErrorEPC = env->PC;
}
+ env->hflags = 0;
env->PC = (int32_t)0xBFC00000;
#if defined (MIPS_USES_R4K_TLB)
env->CP0_Random = MIPS_TLB_NB - 1;
env->CP0_Wired = 0;
/* SMP not implemented */
env->CP0_EBase = 0x80000000;
- env->CP0_Config0 = MIPS_CONFIG0;
- env->CP0_Config1 = MIPS_CONFIG1;
- env->CP0_Config2 = MIPS_CONFIG2;
- env->CP0_Config3 = MIPS_CONFIG3;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
+ /* vectored interrupts not implemented, timer on int 7,
+ no performance counters. */
+ env->CP0_IntCtl = 0xe0000000;
env->CP0_WatchLo = 0;
- env->hflags = MIPS_HFLAG_ERL;
+ env->CP0_WatchHi = 0;
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
- env->CP0_PRid = MIPS_CPU;
#endif
env->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
env->hflags |= MIPS_HFLAG_UM;
env->user_mode_only = 1;
#endif
-#ifdef MIPS_USES_FPU
- env->fcr0 = MIPS_FCR0;
-#endif
- /* XXX some guesswork here, values are CPU specific */
- env->SYNCI_Step = 16;
- env->CCRes = 2;
}
+
+#include "translate_init.c"
projects / qemu.git / blobdiff