PPC: Bump MPIC up to 32 supported CPUs

[qemu.git] / hw / omap_i2c.c

diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index f98ac8d75b81ea542f2bb328bceba845188cd74a..11577b1eecaecf12fe71253f705c579d8a61a247 100644 (file)
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -14,8 +14,7 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "hw.h"
 #include "i2c.h"
@@ -191,8 +190,9 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
             if (s->rxlen > 2)
                 s->fifo >>= 16;
             s->rxlen -= 2;
-        } else
-            /* XXX: remote access (qualifier) error - what's that?  */;
+        } else {
+            /* XXX: remote access (qualifier) error - what's that?  */
+        }
         if (!s->rxlen) {
             s->stat &= ~(1 << 3);                              /* RRDY */
             if (((s->control >> 10) & 1) &&                    /* MST */
@@ -409,13 +409,13 @@ static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_i2c_readfn[] = {
+static CPUReadMemoryFunc * const omap_i2c_readfn[] = {
     omap_badwidth_read16,
     omap_i2c_read,
     omap_badwidth_read16,
 };
 
-static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
+static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
     omap_i2c_writeb,   /* Only the last fifo write can be 8 bit.  */
     omap_i2c_write,
     omap_badwidth_write16,
@@ -426,18 +426,18 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
 {
     int iomemtype;
     struct omap_i2c_s *s = (struct omap_i2c_s *)
-            qemu_mallocz(sizeof(struct omap_i2c_s));
+            g_malloc0(sizeof(struct omap_i2c_s));
 
     /* TODO: set a value greater or equal to real hardware */
     s->revision = 0x11;
     s->irq = irq;
     s->drq[0] = dma[0];
     s->drq[1] = dma[1];
-    s->bus = i2c_init_bus();
+    s->bus = i2c_init_bus(NULL, "i2c");
     omap_i2c_reset(s);
 
-    iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
-                    omap_i2c_writefn, s);
+    iomemtype = cpu_register_io_memory(omap_i2c_readfn,
+                    omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(base, 0x800, iomemtype);
 
     return s;
@@ -448,16 +448,16 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
 {
     int iomemtype;
     struct omap_i2c_s *s = (struct omap_i2c_s *)
-            qemu_mallocz(sizeof(struct omap_i2c_s));
+            g_malloc0(sizeof(struct omap_i2c_s));
 
     s->revision = 0x34;
     s->irq = irq;
     s->drq[0] = dma[0];
     s->drq[1] = dma[1];
-    s->bus = i2c_init_bus();
+    s->bus = i2c_init_bus(NULL, "i2c");
     omap_i2c_reset(s);
 
-    iomemtype = l4_register_io_memory(0, omap_i2c_readfn,
+    iomemtype = l4_register_io_memory(omap_i2c_readfn,
                     omap_i2c_writefn, s);
     omap_l4_attach(ta, 0, iomemtype);