console: Avoid dereferencing NULL active_console

[qemu.git] / hw / arm_gic.c

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index cb774d6e20e5c0ff92530b54246388cdb8ef0c6a..8286a282ea08cb67ca6f146d3862760c187ed0f4 100644 (file)
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -32,6 +32,9 @@ static const uint8_t gic_id[] =
 #define GIC_BASE_IRQ    0
 #endif
 
+#define FROM_SYSBUSGIC(type, dev) \
+    DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
+
 typedef struct gic_irq_state
 {
     /* ??? The documentation seems to imply the enable bits are global, even
@@ -45,6 +48,11 @@ typedef struct gic_irq_state
 } gic_irq_state;
 
 #define ALL_CPU_MASK ((1 << NCPU) - 1)
+#if NCPU > 1
+#define NUM_CPU(s) ((s)->num_cpu)
+#else
+#define NUM_CPU(s) 1
+#endif
 
 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
@@ -74,6 +82,7 @@ typedef struct gic_irq_state
 
 typedef struct gic_state
 {
+    SysBusDevice busdev;
     qemu_irq parent_irq[NCPU];
     int enabled;
     int cpu_enabled[NCPU];
@@ -91,10 +100,11 @@ typedef struct gic_state
     int running_priority[NCPU];
     int current_pending[NCPU];
 
-    qemu_irq *in;
-#ifdef NVIC
-    void *nvic;
+#if NCPU > 1
+    int num_cpu;
 #endif
+
+    int iomemtype;
 } gic_state;
 
 /* TODO: Many places that call this routine could be optimized.  */
@@ -108,7 +118,7 @@ static void gic_update(gic_state *s)
     int cpu;
     int cm;
 
-    for (cpu = 0; cpu < NCPU; cpu++) {
+    for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
         cm = 1 << cpu;
         s->current_pending[cpu] = 1023;
         if (!s->enabled || !s->cpu_enabled[cpu]) {
@@ -254,7 +264,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
         if (offset == 0)
             return s->enabled;
         if (offset == 4)
-            return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5);
+            return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
         if (offset < 0x08)
             return 0;
 #endif
@@ -363,7 +373,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
     uint32_t addr;
     addr = offset;
     if (addr < 0x100 || addr > 0xd00)
-        return nvic_readl(s->nvic, addr);
+        return nvic_readl(s, addr);
 #endif
     val = gic_dist_readw(opaque, offset);
     val |= gic_dist_readw(opaque, offset + 2) << 16;
@@ -523,7 +533,7 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
     uint32_t addr;
     addr = offset;
     if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
-        nvic_writel(s->nvic, addr, value);
+        nvic_writel(s, addr, value);
         return;
     }
 #endif
@@ -557,13 +567,13 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
     gic_dist_writew(opaque, offset + 2, value >> 16);
 }
 
-static CPUReadMemoryFunc *gic_dist_readfn[] = {
+static CPUReadMemoryFunc * const gic_dist_readfn[] = {
    gic_dist_readb,
    gic_dist_readw,
    gic_dist_readl
 };
 
-static CPUWriteMemoryFunc *gic_dist_writefn[] = {
+static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
    gic_dist_writeb,
    gic_dist_writew,
    gic_dist_writel
@@ -597,7 +607,7 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
     switch (offset) {
     case 0x00: /* Control */
         s->cpu_enabled[cpu] = (value & 1);
-        DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis");
+        DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
         break;
     case 0x04: /* Priority mask */
         s->priority_mask[cpu] = (value & 0xff);
@@ -619,7 +629,7 @@ static void gic_reset(gic_state *s)
 {
     int i;
     memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
-    for (i = 0 ; i < NCPU; i++) {
+    for (i = 0 ; i < NUM_CPU(s); i++) {
         s->priority_mask[i] = 0xf0;
         s->current_pending[i] = 1023;
         s->running_irq[i] = 1023;
@@ -650,7 +660,7 @@ static void gic_save(QEMUFile *f, void *opaque)
     int j;
 
     qemu_put_be32(f, s->enabled);
-    for (i = 0; i < NCPU; i++) {
+    for (i = 0; i < NUM_CPU(s); i++) {
         qemu_put_be32(f, s->cpu_enabled[i]);
 #ifndef NVIC
         qemu_put_be32(f, s->irq_target[i]);
@@ -687,7 +697,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
         return -EINVAL;
 
     s->enabled = qemu_get_be32(f);
-    for (i = 0; i < NCPU; i++) {
+    for (i = 0; i < NUM_CPU(s); i++) {
         s->cpu_enabled[i] = qemu_get_be32(f);
 #ifndef NVIC
         s->irq_target[i] = qemu_get_be32(f);
@@ -716,22 +726,23 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
+#if NCPU > 1
+static void gic_init(gic_state *s, int num_cpu)
+#else
+static void gic_init(gic_state *s)
+#endif
 {
-    gic_state *s;
-    int iomemtype;
     int i;
 
-    s = (gic_state *)qemu_mallocz(sizeof(gic_state));
-    s->in = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ);
-    for (i = 0; i < NCPU; i++) {
-        s->parent_irq[i] = parent_irq[i];
+#if NCPU > 1
+    s->num_cpu = num_cpu;
+#endif
+    qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
+    for (i = 0; i < NUM_CPU(s); i++) {
+        sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
     }
-    iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
-                                       gic_dist_writefn, s);
-    cpu_register_physical_memory(dist_base, 0x00001000,
-                                 iomemtype);
+    s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
+                                          gic_dist_writefn, s);
     gic_reset(s);
-    register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
-    return s;
+    register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
 }