* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "hw.h"
-#include "sun4m.h"
-#include "sysemu.h"
-/* debug misc */
-//#define DEBUG_MISC
+#include "sysemu.h"
+#include "sysbus.h"
+#include "trace.h"
/*
* This is the auxio port, chip control and system control part of
* This also includes the PMC CPU idle controller.
*/
-#ifdef DEBUG_MISC
-#define MISC_DPRINTF(fmt, args...) \
-do { printf("MISC: " fmt , ##args); } while (0)
-#else
-#define MISC_DPRINTF(fmt, args...)
-#endif
-
typedef struct MiscState {
+ SysBusDevice busdev;
+ MemoryRegion cfg_iomem;
+ MemoryRegion diag_iomem;
+ MemoryRegion mdm_iomem;
+ MemoryRegion led_iomem;
+ MemoryRegion sysctrl_iomem;
+ MemoryRegion aux1_iomem;
+ MemoryRegion aux2_iomem;
qemu_irq irq;
+ qemu_irq fdc_tc;
+ uint32_t dummy;
uint8_t config;
uint8_t aux1, aux2;
uint8_t diag, mctrl;
- uint32_t sysctrl;
+ uint8_t sysctrl;
uint16_t leds;
- CPUState *env;
} MiscState;
+typedef struct APCState {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ qemu_irq cpu_halt;
+} APCState;
+
#define MISC_SIZE 1
-#define SYSCTRL_MAXADDR 3
-#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
-#define LED_MAXADDR 1
-#define LED_SIZE (LED_MAXADDR + 1)
-
-#define MISC_MASK 0x0fff0000
-#define MISC_LEDS 0x01600000
-#define MISC_CFG 0x01800000
-#define MISC_DIAG 0x01a00000
-#define MISC_MDM 0x01b00000
-#define MISC_SYS 0x01f00000
+#define SYSCTRL_SIZE 4
+
+#define AUX1_TC 0x02
#define AUX2_PWROFF 0x01
#define AUX2_PWRINTCLR 0x02
MiscState *s = opaque;
if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
- MISC_DPRINTF("Raise IRQ\n");
+ trace_slavio_misc_update_irq_raise();
qemu_irq_raise(s->irq);
} else {
- MISC_DPRINTF("Lower IRQ\n");
+ trace_slavio_misc_update_irq_lower();
qemu_irq_lower(s->irq);
}
}
-static void slavio_misc_reset(void *opaque)
+static void slavio_misc_reset(DeviceState *d)
{
- MiscState *s = opaque;
+ MiscState *s = container_of(d, MiscState, busdev.qdev);
// Diagnostic and system control registers not cleared in reset
s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}
-void slavio_set_power_fail(void *opaque, int power_failing)
+static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
{
MiscState *s = opaque;
- MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
+ trace_slavio_set_power_fail(power_failing, s->config);
if (power_failing && (s->config & CFG_PWRINTEN)) {
s->aux2 |= AUX2_PWRFAIL;
} else {
slavio_misc_update_irq(s);
}
-static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
MiscState *s = opaque;
- switch (addr & MISC_MASK) {
- case MISC_CFG:
- MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
- s->config = val & 0xff;
- slavio_misc_update_irq(s);
- break;
- case MISC_DIAG:
- MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
- s->diag = val & 0xff;
- break;
- case MISC_MDM:
- MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
- s->mctrl = val & 0xff;
- break;
- default:
- break;
- }
+ trace_slavio_cfg_mem_writeb(val & 0xff);
+ s->config = val & 0xff;
+ slavio_misc_update_irq(s);
}
-static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MiscState *s = opaque;
uint32_t ret = 0;
- switch (addr & MISC_MASK) {
- case MISC_CFG:
- ret = s->config;
- MISC_DPRINTF("Read config %2.2x\n", ret);
- break;
- case MISC_DIAG:
- ret = s->diag;
- MISC_DPRINTF("Read diag %2.2x\n", ret);
- break;
- case MISC_MDM:
- ret = s->mctrl;
- MISC_DPRINTF("Read modem control %2.2x\n", ret);
- break;
- default:
- break;
- }
+ ret = s->config;
+ trace_slavio_cfg_mem_readb(ret);
return ret;
}
-static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
- slavio_misc_mem_readb,
- NULL,
- NULL,
+static const MemoryRegionOps slavio_cfg_mem_ops = {
+ .read = slavio_cfg_mem_readb,
+ .write = slavio_cfg_mem_writeb,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
-static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
- slavio_misc_mem_writeb,
- NULL,
- NULL,
+static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ MiscState *s = opaque;
+
+ trace_slavio_diag_mem_writeb(val & 0xff);
+ s->diag = val & 0xff;
+}
+
+static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ ret = s->diag;
+ trace_slavio_diag_mem_readb(ret);
+ return ret;
+}
+
+static const MemoryRegionOps slavio_diag_mem_ops = {
+ .read = slavio_diag_mem_readb,
+ .write = slavio_diag_mem_writeb,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ MiscState *s = opaque;
+
+ trace_slavio_mdm_mem_writeb(val & 0xff);
+ s->mctrl = val & 0xff;
+}
+
+static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ ret = s->mctrl;
+ trace_slavio_mdm_mem_readb(ret);
+ return ret;
+}
+
+static const MemoryRegionOps slavio_mdm_mem_ops = {
+ .read = slavio_mdm_mem_readb,
+ .write = slavio_mdm_mem_writeb,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
MiscState *s = opaque;
- MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
+ trace_slavio_aux1_mem_writeb(val & 0xff);
+ if (val & AUX1_TC) {
+ // Send a pulse to floppy terminal count line
+ if (s->fdc_tc) {
+ qemu_irq_raise(s->fdc_tc);
+ qemu_irq_lower(s->fdc_tc);
+ }
+ val &= ~AUX1_TC;
+ }
s->aux1 = val & 0xff;
}
-static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MiscState *s = opaque;
uint32_t ret = 0;
ret = s->aux1;
- MISC_DPRINTF("Read aux1 %2.2x\n", ret);
-
+ trace_slavio_aux1_mem_readb(ret);
return ret;
}
-static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
- slavio_aux1_mem_readb,
- NULL,
- NULL,
-};
-
-static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
- slavio_aux1_mem_writeb,
- NULL,
- NULL,
+static const MemoryRegionOps slavio_aux1_mem_ops = {
+ .read = slavio_aux1_mem_readb,
+ .write = slavio_aux1_mem_writeb,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
MiscState *s = opaque;
val &= AUX2_PWRINTCLR | AUX2_PWROFF;
- MISC_DPRINTF("Write aux2 %2.2x\n", val);
+ trace_slavio_aux2_mem_writeb(val & 0xff);
val |= s->aux2 & AUX2_PWRFAIL;
if (val & AUX2_PWRINTCLR) // Clear Power Fail int
val &= AUX2_PWROFF;
slavio_misc_update_irq(s);
}
-static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MiscState *s = opaque;
uint32_t ret = 0;
ret = s->aux2;
- MISC_DPRINTF("Read aux2 %2.2x\n", ret);
-
+ trace_slavio_aux2_mem_readb(ret);
return ret;
}
-static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
- slavio_aux2_mem_readb,
- NULL,
- NULL,
-};
-
-static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
- slavio_aux2_mem_writeb,
- NULL,
- NULL,
+static const MemoryRegionOps slavio_aux2_mem_ops = {
+ .read = slavio_aux2_mem_readb,
+ .write = slavio_aux2_mem_writeb,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
-static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- MiscState *s = opaque;
+ APCState *s = opaque;
- MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
- cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
+ trace_apc_mem_writeb(val & 0xff);
+ qemu_irq_raise(s->cpu_halt);
}
-static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t ret = 0;
- MISC_DPRINTF("Read power management %2.2x\n", ret);
+ trace_apc_mem_readb(ret);
return ret;
}
-static CPUReadMemoryFunc *apc_mem_read[3] = {
- apc_mem_readb,
- NULL,
- NULL,
-};
-
-static CPUWriteMemoryFunc *apc_mem_write[3] = {
- apc_mem_writeb,
- NULL,
- NULL,
+static const MemoryRegionOps apc_mem_ops = {
+ .read = apc_mem_readb,
+ .write = apc_mem_writeb,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ }
};
-static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MiscState *s = opaque;
- uint32_t ret = 0, saddr;
+ uint32_t ret = 0;
- saddr = addr & SYSCTRL_MAXADDR;
- switch (saddr) {
+ switch (addr) {
case 0:
ret = s->sysctrl;
break;
default:
break;
}
- MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
- ret);
+ trace_slavio_sysctrl_mem_readl(ret);
return ret;
}
static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
MiscState *s = opaque;
- uint32_t saddr;
- saddr = addr & SYSCTRL_MAXADDR;
- MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
- val);
- switch (saddr) {
+ trace_slavio_sysctrl_mem_writel(val);
+ switch (addr) {
case 0:
if (val & SYS_RESET) {
s->sysctrl = SYS_RESETSTAT;
}
}
-static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
- NULL,
- NULL,
- slavio_sysctrl_mem_readl,
-};
-
-static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
- NULL,
- NULL,
- slavio_sysctrl_mem_writel,
+static const MemoryRegionOps slavio_sysctrl_mem_ops = {
+ .read = slavio_sysctrl_mem_readl,
+ .write = slavio_sysctrl_mem_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MiscState *s = opaque;
- uint32_t ret = 0, saddr;
+ uint32_t ret = 0;
- saddr = addr & LED_MAXADDR;
- switch (saddr) {
+ switch (addr) {
case 0:
ret = s->leds;
break;
default:
break;
}
- MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
- ret);
+ trace_slavio_led_mem_readw(ret);
return ret;
}
static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
MiscState *s = opaque;
- uint32_t saddr;
- saddr = addr & LED_MAXADDR;
- MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
- val);
- switch (saddr) {
+ trace_slavio_led_mem_readw(val & 0xffff);
+ switch (addr) {
case 0:
s->leds = val;
break;
}
}
-static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
- NULL,
- slavio_led_mem_readw,
- NULL,
+static const MemoryRegionOps slavio_led_mem_ops = {
+ .read = slavio_led_mem_readw,
+ .write = slavio_led_mem_writew,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 2,
+ .max_access_size = 2,
+ },
};
-static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
- NULL,
- slavio_led_mem_writew,
- NULL,
+static const VMStateDescription vmstate_misc = {
+ .name ="slavio_misc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(dummy, MiscState),
+ VMSTATE_UINT8(config, MiscState),
+ VMSTATE_UINT8(aux1, MiscState),
+ VMSTATE_UINT8(aux2, MiscState),
+ VMSTATE_UINT8(diag, MiscState),
+ VMSTATE_UINT8(mctrl, MiscState),
+ VMSTATE_UINT8(sysctrl, MiscState),
+ VMSTATE_END_OF_LIST()
+ }
};
-static void slavio_misc_save(QEMUFile *f, void *opaque)
+static int apc_init1(SysBusDevice *dev)
{
- MiscState *s = opaque;
- int tmp;
- uint8_t tmp8;
-
- tmp = 0;
- qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
- qemu_put_8s(f, &s->config);
- qemu_put_8s(f, &s->aux1);
- qemu_put_8s(f, &s->aux2);
- qemu_put_8s(f, &s->diag);
- qemu_put_8s(f, &s->mctrl);
- tmp8 = s->sysctrl & 0xff;
- qemu_put_8s(f, &tmp8);
+ APCState *s = FROM_SYSBUS(APCState, dev);
+
+ sysbus_init_irq(dev, &s->cpu_halt);
+
+ /* Power management (APC) XXX: not a Slavio device */
+ memory_region_init_io(&s->iomem, &apc_mem_ops, s,
+ "apc", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->iomem);
+ return 0;
}
-static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
+static int slavio_misc_init1(SysBusDevice *dev)
{
- MiscState *s = opaque;
- int tmp;
- uint8_t tmp8;
-
- if (version_id != 1)
- return -EINVAL;
-
- qemu_get_be32s(f, &tmp);
- qemu_get_8s(f, &s->config);
- qemu_get_8s(f, &s->aux1);
- qemu_get_8s(f, &s->aux2);
- qemu_get_8s(f, &s->diag);
- qemu_get_8s(f, &s->mctrl);
- qemu_get_8s(f, &tmp8);
- s->sysctrl = (uint32_t)tmp8;
+ MiscState *s = FROM_SYSBUS(MiscState, dev);
+
+ sysbus_init_irq(dev, &s->irq);
+ sysbus_init_irq(dev, &s->fdc_tc);
+
+ /* 8 bit registers */
+ /* Slavio control */
+ memory_region_init_io(&s->cfg_iomem, &slavio_cfg_mem_ops, s,
+ "configuration", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->cfg_iomem);
+
+ /* Diagnostics */
+ memory_region_init_io(&s->diag_iomem, &slavio_diag_mem_ops, s,
+ "diagnostic", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->diag_iomem);
+
+ /* Modem control */
+ memory_region_init_io(&s->mdm_iomem, &slavio_mdm_mem_ops, s,
+ "modem", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->mdm_iomem);
+
+ /* 16 bit registers */
+ /* ss600mp diag LEDs */
+ memory_region_init_io(&s->led_iomem, &slavio_led_mem_ops, s,
+ "leds", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->led_iomem);
+
+ /* 32 bit registers */
+ /* System control */
+ memory_region_init_io(&s->sysctrl_iomem, &slavio_sysctrl_mem_ops, s,
+ "system-control", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->sysctrl_iomem);
+
+ /* AUX 1 (Misc System Functions) */
+ memory_region_init_io(&s->aux1_iomem, &slavio_aux1_mem_ops, s,
+ "misc-system-functions", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->aux1_iomem);
+
+ /* AUX 2 (Software Powerdown Control) */
+ memory_region_init_io(&s->aux2_iomem, &slavio_aux2_mem_ops, s,
+ "software-powerdown-control", MISC_SIZE);
+ sysbus_init_mmio(dev, &s->aux2_iomem);
+
+ qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
+
return 0;
}
-void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
- target_phys_addr_t aux1_base,
- target_phys_addr_t aux2_base, qemu_irq irq,
- CPUState *env)
+static void slavio_misc_class_init(ObjectClass *klass, void *data)
{
- int io;
- MiscState *s;
-
- s = qemu_mallocz(sizeof(MiscState));
- if (!s)
- return NULL;
-
- if (base) {
- /* 8 bit registers */
- io = cpu_register_io_memory(0, slavio_misc_mem_read,
- slavio_misc_mem_write, s);
- // Slavio control
- cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
- // Diagnostics
- cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
- // Modem control
- cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
-
- /* 16 bit registers */
- io = cpu_register_io_memory(0, slavio_led_mem_read,
- slavio_led_mem_write, s);
- /* ss600mp diag LEDs */
- cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
-
- /* 32 bit registers */
- io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
- slavio_sysctrl_mem_write, s);
- // System control
- cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
- }
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- // AUX 1 (Misc System Functions)
- if (aux1_base) {
- io = cpu_register_io_memory(0, slavio_aux1_mem_read,
- slavio_aux1_mem_write, s);
- cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
- }
+ k->init = slavio_misc_init1;
+ dc->reset = slavio_misc_reset;
+ dc->vmsd = &vmstate_misc;
+}
- // AUX 2 (Software Powerdown Control)
- if (aux2_base) {
- io = cpu_register_io_memory(0, slavio_aux2_mem_read,
- slavio_aux2_mem_write, s);
- cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
- }
+static TypeInfo slavio_misc_info = {
+ .name = "slavio_misc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MiscState),
+ .class_init = slavio_misc_class_init,
+};
- // Power management (APC) XXX: not a Slavio device
- if (power_base) {
- io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
- cpu_register_physical_memory(power_base, MISC_SIZE, io);
- }
+static void apc_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- s->irq = irq;
- s->env = env;
+ k->init = apc_init1;
+}
- register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
- s);
- qemu_register_reset(slavio_misc_reset, s);
- slavio_misc_reset(s);
+static TypeInfo apc_info = {
+ .name = "apc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MiscState),
+ .class_init = apc_class_init,
+};
- return s;
+static void slavio_misc_register_types(void)
+{
+ type_register_static(&slavio_misc_info);
+ type_register_static(&apc_info);
}
+
+type_init(slavio_misc_register_types)
projects / qemu.git / blobdiff