hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen.h"
  33 #include "hw/pam.h"
  34 #include "sysemu/sysemu.h"
  35
  36 /*
  37  * I440FX chipset data sheet.
  38  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  39  */
  40
  41 typedef struct I440FXState {
  42     PCIHostState parent_obj;
  43 } I440FXState;
  44
  45 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  46 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  47 #define XEN_PIIX_NUM_PIRQS      128ULL
  48 #define PIIX_PIRQC              0x60
  49
  50 /*
  51  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  52  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  53  */
  54 #define RCR_IOPORT 0xcf9
  55
  56 typedef struct PIIX3State {
  57     PCIDevice dev;
  58
  59     /*
  60      * bitmap to track pic levels.
  61      * The pic level is the logical OR of all the PCI irqs mapped to it
  62      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  63      *
  64      * PIRQ is mapped to PIC pins, we track it by
  65      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  66      * pic_irq * PIIX_NUM_PIRQS + pirq
  67      */
  68 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  69 #error "unable to encode pic state in 64bit in pic_levels."
  70 #endif
  71     uint64_t pic_levels;
  72
  73     qemu_irq *pic;
  74
  75     /* This member isn't used. Just for save/load compatibility */
  76     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  77
  78     /* Reset Control Register contents */
  79     uint8_t rcr;
  80
  81     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  82     MemoryRegion rcr_mem;
  83 } PIIX3State;
  84
  85 struct PCII440FXState {
  86     PCIDevice dev;
  87     MemoryRegion *system_memory;
  88     MemoryRegion *pci_address_space;
  89     MemoryRegion *ram_memory;
  90     MemoryRegion pci_hole;
  91     MemoryRegion pci_hole_64bit;
  92     PAMMemoryRegion pam_regions[13];
  93     MemoryRegion smram_region;
  94     uint8_t smm_enabled;
  95 };
  96
  97
  98 #define I440FX_PAM      0x59
  99 #define I440FX_PAM_SIZE 7
 100 #define I440FX_SMRAM    0x72
 101
 102 static void piix3_set_irq(void *opaque, int pirq, int level);
 103 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 104 static void piix3_write_config_xen(PCIDevice *dev,
 105                                uint32_t address, uint32_t val, int len);
 106
 107 /* return the global irq number corresponding to a given device irq
 108    pin. We could also use the bus number to have a more precise
 109    mapping. */
 110 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 111 {
 112     int slot_addend;
 113     slot_addend = (pci_dev->devfn >> 3) - 1;
 114     return (pci_intx + slot_addend) & 3;
 115 }
 116
 117 static void i440fx_update_memory_mappings(PCII440FXState *d)
 118 {
 119     int i;
 120
 121     memory_region_transaction_begin();
 122     for (i = 0; i < 13; i++) {
 123         pam_update(&d->pam_regions[i], i,
 124                    d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
 125     }
 126     smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
 127     memory_region_transaction_commit();
 128 }
 129
 130 static void i440fx_set_smm(int val, void *arg)
 131 {
 132     PCII440FXState *d = arg;
 133
 134     memory_region_transaction_begin();
 135     smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
 136                   &d->smram_region);
 137     memory_region_transaction_commit();
 138 }
 139
 140
 141 static void i440fx_write_config(PCIDevice *dev,
 142                                 uint32_t address, uint32_t val, int len)
 143 {
 144     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 145
 146     /* XXX: implement SMRAM.D_LOCK */
 147     pci_default_write_config(dev, address, val, len);
 148     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 149         range_covers_byte(address, len, I440FX_SMRAM)) {
 150         i440fx_update_memory_mappings(d);
 151     }
 152 }
 153
 154 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 155 {
 156     PCII440FXState *d = opaque;
 157     int ret, i;
 158
 159     ret = pci_device_load(&d->dev, f);
 160     if (ret < 0)
 161         return ret;
 162     i440fx_update_memory_mappings(d);
 163     qemu_get_8s(f, &d->smm_enabled);
 164
 165     if (version_id == 2) {
 166         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 167             qemu_get_be32(f); /* dummy load for compatibility */
 168         }
 169     }
 170
 171     return 0;
 172 }
 173
 174 static int i440fx_post_load(void *opaque, int version_id)
 175 {
 176     PCII440FXState *d = opaque;
 177
 178     i440fx_update_memory_mappings(d);
 179     return 0;
 180 }
 181
 182 static const VMStateDescription vmstate_i440fx = {
 183     .name = "I440FX",
 184     .version_id = 3,
 185     .minimum_version_id = 3,
 186     .minimum_version_id_old = 1,
 187     .load_state_old = i440fx_load_old,
 188     .post_load = i440fx_post_load,
 189     .fields      = (VMStateField []) {
 190         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 191         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 192         VMSTATE_END_OF_LIST()
 193     }
 194 };
 195
 196 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 197 {
 198     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 199
 200     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 201                           "pci-conf-idx", 4);
 202     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 203     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 204
 205     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 206                           "pci-conf-data", 4);
 207     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 208     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 209
 210     return 0;
 211 }
 212
 213 static int i440fx_initfn(PCIDevice *dev)
 214 {
 215     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 216
 217     d->dev.config[I440FX_SMRAM] = 0x02;
 218
 219     cpu_smm_register(&i440fx_set_smm, d);
 220     return 0;
 221 }
 222
 223 static PCIBus *i440fx_common_init(const char *device_name,
 224                                   PCII440FXState **pi440fx_state,
 225                                   int *piix3_devfn,
 226                                   ISABus **isa_bus, qemu_irq *pic,
 227                                   MemoryRegion *address_space_mem,
 228                                   MemoryRegion *address_space_io,
 229                                   ram_addr_t ram_size,
 230                                   hwaddr pci_hole_start,
 231                                   hwaddr pci_hole_size,
 232                                   hwaddr pci_hole64_start,
 233                                   hwaddr pci_hole64_size,
 234                                   MemoryRegion *pci_address_space,
 235                                   MemoryRegion *ram_memory)
 236 {
 237     DeviceState *dev;
 238     PCIBus *b;
 239     PCIDevice *d;
 240     PCIHostState *s;
 241     PIIX3State *piix3;
 242     PCII440FXState *f;
 243     unsigned i;
 244
 245     dev = qdev_create(NULL, "i440FX-pcihost");
 246     s = PCI_HOST_BRIDGE(dev);
 247     b = pci_bus_new(dev, NULL, pci_address_space,
 248                     address_space_io, 0, TYPE_PCI_BUS);
 249     s->bus = b;
 250     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 251     qdev_init_nofail(dev);
 252
 253     d = pci_create_simple(b, 0, device_name);
 254     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 255     f = *pi440fx_state;
 256     f->system_memory = address_space_mem;
 257     f->pci_address_space = pci_address_space;
 258     f->ram_memory = ram_memory;
 259     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 260                              pci_hole_start, pci_hole_size);
 261     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 262     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 263                              f->pci_address_space,
 264                              pci_hole64_start, pci_hole64_size);
 265     if (pci_hole64_size) {
 266         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 267                                     &f->pci_hole_64bit);
 268     }
 269     memory_region_init_alias(&f->smram_region, "smram-region",
 270                              f->pci_address_space, 0xa0000, 0x20000);
 271     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 272                                         &f->smram_region, 1);
 273     memory_region_set_enabled(&f->smram_region, false);
 274     init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
 275              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 276     for (i = 0; i < 12; ++i) {
 277         init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
 278                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 279                  PAM_EXPAN_SIZE);
 280     }
 281
 282     /* Xen supports additional interrupt routes from the PCI devices to
 283      * the IOAPIC: the four pins of each PCI device on the bus are also
 284      * connected to the IOAPIC directly.
 285      * These additional routes can be discovered through ACPI. */
 286     if (xen_enabled()) {
 287         piix3 = DO_UPCAST(PIIX3State, dev,
 288                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 289         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 290                 piix3, XEN_PIIX_NUM_PIRQS);
 291     } else {
 292         piix3 = DO_UPCAST(PIIX3State, dev,
 293                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 294         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 295                 PIIX_NUM_PIRQS);
 296         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 297     }
 298     piix3->pic = pic;
 299     *isa_bus = DO_UPCAST(ISABus, qbus,
 300                          qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
 301
 302     *piix3_devfn = piix3->dev.devfn;
 303
 304     ram_size = ram_size / 8 / 1024 / 1024;
 305     if (ram_size > 255)
 306         ram_size = 255;
 307     (*pi440fx_state)->dev.config[0x57]=ram_size;
 308
 309     i440fx_update_memory_mappings(f);
 310
 311     return b;
 312 }
 313
 314 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 315                     ISABus **isa_bus, qemu_irq *pic,
 316                     MemoryRegion *address_space_mem,
 317                     MemoryRegion *address_space_io,
 318                     ram_addr_t ram_size,
 319                     hwaddr pci_hole_start,
 320                     hwaddr pci_hole_size,
 321                     hwaddr pci_hole64_start,
 322                     hwaddr pci_hole64_size,
 323                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 324
 325 {
 326     PCIBus *b;
 327
 328     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
 329                            address_space_mem, address_space_io, ram_size,
 330                            pci_hole_start, pci_hole_size,
 331                            pci_hole64_start, pci_hole64_size,
 332                            pci_memory, ram_memory);
 333     return b;
 334 }
 335
 336 /* PIIX3 PCI to ISA bridge */
 337 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 338 {
 339     qemu_set_irq(piix3->pic[pic_irq],
 340                  !!(piix3->pic_levels &
 341                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 342                      (pic_irq * PIIX_NUM_PIRQS))));
 343 }
 344
 345 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 346 {
 347     int pic_irq;
 348     uint64_t mask;
 349
 350     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 351     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 352         return;
 353     }
 354
 355     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 356     piix3->pic_levels &= ~mask;
 357     piix3->pic_levels |= mask * !!level;
 358
 359     piix3_set_irq_pic(piix3, pic_irq);
 360 }
 361
 362 static void piix3_set_irq(void *opaque, int pirq, int level)
 363 {
 364     PIIX3State *piix3 = opaque;
 365     piix3_set_irq_level(piix3, pirq, level);
 366 }
 367
 368 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 369 {
 370     PIIX3State *piix3 = opaque;
 371     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 372     PCIINTxRoute route;
 373
 374     if (irq < PIIX_NUM_PIC_IRQS) {
 375         route.mode = PCI_INTX_ENABLED;
 376         route.irq = irq;
 377     } else {
 378         route.mode = PCI_INTX_DISABLED;
 379         route.irq = -1;
 380     }
 381     return route;
 382 }
 383
 384 /* irq routing is changed. so rebuild bitmap */
 385 static void piix3_update_irq_levels(PIIX3State *piix3)
 386 {
 387     int pirq;
 388
 389     piix3->pic_levels = 0;
 390     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 391         piix3_set_irq_level(piix3, pirq,
 392                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 393     }
 394 }
 395
 396 static void piix3_write_config(PCIDevice *dev,
 397                                uint32_t address, uint32_t val, int len)
 398 {
 399     pci_default_write_config(dev, address, val, len);
 400     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 401         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 402         int pic_irq;
 403
 404         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 405         piix3_update_irq_levels(piix3);
 406         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 407             piix3_set_irq_pic(piix3, pic_irq);
 408         }
 409     }
 410 }
 411
 412 static void piix3_write_config_xen(PCIDevice *dev,
 413                                uint32_t address, uint32_t val, int len)
 414 {
 415     xen_piix_pci_write_config_client(address, val, len);
 416     piix3_write_config(dev, address, val, len);
 417 }
 418
 419 static void piix3_reset(void *opaque)
 420 {
 421     PIIX3State *d = opaque;
 422     uint8_t *pci_conf = d->dev.config;
 423
 424     pci_conf[0x04] = 0x07; // master, memory and I/O
 425     pci_conf[0x05] = 0x00;
 426     pci_conf[0x06] = 0x00;
 427     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 428     pci_conf[0x4c] = 0x4d;
 429     pci_conf[0x4e] = 0x03;
 430     pci_conf[0x4f] = 0x00;
 431     pci_conf[0x60] = 0x80;
 432     pci_conf[0x61] = 0x80;
 433     pci_conf[0x62] = 0x80;
 434     pci_conf[0x63] = 0x80;
 435     pci_conf[0x69] = 0x02;
 436     pci_conf[0x70] = 0x80;
 437     pci_conf[0x76] = 0x0c;
 438     pci_conf[0x77] = 0x0c;
 439     pci_conf[0x78] = 0x02;
 440     pci_conf[0x79] = 0x00;
 441     pci_conf[0x80] = 0x00;
 442     pci_conf[0x82] = 0x00;
 443     pci_conf[0xa0] = 0x08;
 444     pci_conf[0xa2] = 0x00;
 445     pci_conf[0xa3] = 0x00;
 446     pci_conf[0xa4] = 0x00;
 447     pci_conf[0xa5] = 0x00;
 448     pci_conf[0xa6] = 0x00;
 449     pci_conf[0xa7] = 0x00;
 450     pci_conf[0xa8] = 0x0f;
 451     pci_conf[0xaa] = 0x00;
 452     pci_conf[0xab] = 0x00;
 453     pci_conf[0xac] = 0x00;
 454     pci_conf[0xae] = 0x00;
 455
 456     d->pic_levels = 0;
 457     d->rcr = 0;
 458 }
 459
 460 static int piix3_post_load(void *opaque, int version_id)
 461 {
 462     PIIX3State *piix3 = opaque;
 463     piix3_update_irq_levels(piix3);
 464     return 0;
 465 }
 466
 467 static void piix3_pre_save(void *opaque)
 468 {
 469     int i;
 470     PIIX3State *piix3 = opaque;
 471
 472     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 473         piix3->pci_irq_levels_vmstate[i] =
 474             pci_bus_get_irq_level(piix3->dev.bus, i);
 475     }
 476 }
 477
 478 static bool piix3_rcr_needed(void *opaque)
 479 {
 480     PIIX3State *piix3 = opaque;
 481
 482     return (piix3->rcr != 0);
 483 }
 484
 485 static const VMStateDescription vmstate_piix3_rcr = {
 486     .name = "PIIX3/rcr",
 487     .version_id = 1,
 488     .minimum_version_id = 1,
 489     .fields = (VMStateField []) {
 490         VMSTATE_UINT8(rcr, PIIX3State),
 491         VMSTATE_END_OF_LIST()
 492     }
 493 };
 494
 495 static const VMStateDescription vmstate_piix3 = {
 496     .name = "PIIX3",
 497     .version_id = 3,
 498     .minimum_version_id = 2,
 499     .minimum_version_id_old = 2,
 500     .post_load = piix3_post_load,
 501     .pre_save = piix3_pre_save,
 502     .fields      = (VMStateField[]) {
 503         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 504         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 505                               PIIX_NUM_PIRQS, 3),
 506         VMSTATE_END_OF_LIST()
 507     },
 508     .subsections = (VMStateSubsection[]) {
 509         {
 510             .vmsd = &vmstate_piix3_rcr,
 511             .needed = piix3_rcr_needed,
 512         },
 513         { 0 }
 514     }
 515 };
 516
 517
 518 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 519 {
 520     PIIX3State *d = opaque;
 521
 522     if (val & 4) {
 523         qemu_system_reset_request();
 524         return;
 525     }
 526     d->rcr = val & 2; /* keep System Reset type only */
 527 }
 528
 529 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 530 {
 531     PIIX3State *d = opaque;
 532
 533     return d->rcr;
 534 }
 535
 536 static const MemoryRegionOps rcr_ops = {
 537     .read = rcr_read,
 538     .write = rcr_write,
 539     .endianness = DEVICE_LITTLE_ENDIAN
 540 };
 541
 542 static int piix3_initfn(PCIDevice *dev)
 543 {
 544     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 545
 546     isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
 547
 548     memory_region_init_io(&d->rcr_mem, &rcr_ops, d, "piix3-reset-control", 1);
 549     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 550                                         &d->rcr_mem, 1);
 551
 552     qemu_register_reset(piix3_reset, d);
 553     return 0;
 554 }
 555
 556 static void piix3_class_init(ObjectClass *klass, void *data)
 557 {
 558     DeviceClass *dc = DEVICE_CLASS(klass);
 559     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 560
 561     dc->desc        = "ISA bridge";
 562     dc->vmsd        = &vmstate_piix3;
 563     dc->no_user     = 1,
 564     k->no_hotplug   = 1;
 565     k->init         = piix3_initfn;
 566     k->config_write = piix3_write_config;
 567     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 568     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 569     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 570 }
 571
 572 static const TypeInfo piix3_info = {
 573     .name          = "PIIX3",
 574     .parent        = TYPE_PCI_DEVICE,
 575     .instance_size = sizeof(PIIX3State),
 576     .class_init    = piix3_class_init,
 577 };
 578
 579 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 580 {
 581     DeviceClass *dc = DEVICE_CLASS(klass);
 582     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 583
 584     dc->desc        = "ISA bridge";
 585     dc->vmsd        = &vmstate_piix3;
 586     dc->no_user     = 1;
 587     k->no_hotplug   = 1;
 588     k->init         = piix3_initfn;
 589     k->config_write = piix3_write_config_xen;
 590     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 591     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 592     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 593 };
 594
 595 static const TypeInfo piix3_xen_info = {
 596     .name          = "PIIX3-xen",
 597     .parent        = TYPE_PCI_DEVICE,
 598     .instance_size = sizeof(PIIX3State),
 599     .class_init    = piix3_xen_class_init,
 600 };
 601
 602 static void i440fx_class_init(ObjectClass *klass, void *data)
 603 {
 604     DeviceClass *dc = DEVICE_CLASS(klass);
 605     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 606
 607     k->no_hotplug = 1;
 608     k->init = i440fx_initfn;
 609     k->config_write = i440fx_write_config;
 610     k->vendor_id = PCI_VENDOR_ID_INTEL;
 611     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 612     k->revision = 0x02;
 613     k->class_id = PCI_CLASS_BRIDGE_HOST;
 614     dc->desc = "Host bridge";
 615     dc->no_user = 1;
 616     dc->vmsd = &vmstate_i440fx;
 617 }
 618
 619 static const TypeInfo i440fx_info = {
 620     .name          = "i440FX",
 621     .parent        = TYPE_PCI_DEVICE,
 622     .instance_size = sizeof(PCII440FXState),
 623     .class_init    = i440fx_class_init,
 624 };
 625
 626 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 627 {
 628     DeviceClass *dc = DEVICE_CLASS(klass);
 629     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 630
 631     k->init = i440fx_pcihost_initfn;
 632     dc->fw_name = "pci";
 633     dc->no_user = 1;
 634 }
 635
 636 static const TypeInfo i440fx_pcihost_info = {
 637     .name          = "i440FX-pcihost",
 638     .parent        = TYPE_PCI_HOST_BRIDGE,
 639     .instance_size = sizeof(I440FXState),
 640     .class_init    = i440fx_pcihost_class_init,
 641 };
 642
 643 static void i440fx_register_types(void)
 644 {
 645     type_register_static(&i440fx_info);
 646     type_register_static(&piix3_info);
 647     type_register_static(&piix3_xen_info);
 648     type_register_static(&i440fx_pcihost_info);
 649 }
 650
 651 type_init(i440fx_register_types)