target/arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/error-report.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "qemu-common.h"
  27 #include "exec/exec-all.h"
  28 #include "hw/qdev-properties.h"
  29 #if !defined(CONFIG_USER_ONLY)
  30 #include "hw/loader.h"
  31 #endif
  32 #include "hw/arm/arm.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/hw_accel.h"
  35 #include "kvm_arm.h"
  36
  37 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  38 {
  39     ARMCPU *cpu = ARM_CPU(cs);
  40
  41     cpu->env.regs[15] = value;
  42 }
  43
  44 static bool arm_cpu_has_work(CPUState *cs)
  45 {
  46     ARMCPU *cpu = ARM_CPU(cs);
  47
  48     return (cpu->power_state != PSCI_OFF)
  49         && cs->interrupt_request &
  50         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  51          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  52          | CPU_INTERRUPT_EXITTB);
  53 }
  54
  55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
  56                                  void *opaque)
  57 {
  58     /* We currently only support registering a single hook function */
  59     assert(!cpu->el_change_hook);
  60     cpu->el_change_hook = hook;
  61     cpu->el_change_hook_opaque = opaque;
  62 }
  63
  64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  65 {
  66     /* Reset a single ARMCPRegInfo register */
  67     ARMCPRegInfo *ri = value;
  68     ARMCPU *cpu = opaque;
  69
  70     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  71         return;
  72     }
  73
  74     if (ri->resetfn) {
  75         ri->resetfn(&cpu->env, ri);
  76         return;
  77     }
  78
  79     /* A zero offset is never possible as it would be regs[0]
  80      * so we use it to indicate that reset is being handled elsewhere.
  81      * This is basically only used for fields in non-core coprocessors
  82      * (like the pxa2xx ones).
  83      */
  84     if (!ri->fieldoffset) {
  85         return;
  86     }
  87
  88     if (cpreg_field_is_64bit(ri)) {
  89         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  90     } else {
  91         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  92     }
  93 }
  94
  95 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  96 {
  97     /* Purely an assertion check: we've already done reset once,
  98      * so now check that running the reset for the cpreg doesn't
  99      * change its value. This traps bugs where two different cpregs
 100      * both try to reset the same state field but to different values.
 101      */
 102     ARMCPRegInfo *ri = value;
 103     ARMCPU *cpu = opaque;
 104     uint64_t oldvalue, newvalue;
 105
 106     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 107         return;
 108     }
 109
 110     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 111     cp_reg_reset(key, value, opaque);
 112     newvalue = read_raw_cp_reg(&cpu->env, ri);
 113     assert(oldvalue == newvalue);
 114 }
 115
 116 /* CPUClass::reset() */
 117 static void arm_cpu_reset(CPUState *s)
 118 {
 119     ARMCPU *cpu = ARM_CPU(s);
 120     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 121     CPUARMState *env = &cpu->env;
 122
 123     acc->parent_reset(s);
 124
 125     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 126
 127     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 128     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 129
 130     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 131     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 132     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 133     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 134
 135     cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
 136     s->halted = cpu->start_powered_off;
 137
 138     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 139         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 140     }
 141
 142     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 143         /* 64 bit CPUs always start in 64 bit mode */
 144         env->aarch64 = 1;
 145 #if defined(CONFIG_USER_ONLY)
 146         env->pstate = PSTATE_MODE_EL0t;
 147         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 148         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 149         /* and to the FP/Neon instructions */
 150         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 151 #else
 152         /* Reset into the highest available EL */
 153         if (arm_feature(env, ARM_FEATURE_EL3)) {
 154             env->pstate = PSTATE_MODE_EL3h;
 155         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 156             env->pstate = PSTATE_MODE_EL2h;
 157         } else {
 158             env->pstate = PSTATE_MODE_EL1h;
 159         }
 160         env->pc = cpu->rvbar;
 161 #endif
 162     } else {
 163 #if defined(CONFIG_USER_ONLY)
 164         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 165         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 166 #endif
 167     }
 168
 169 #if defined(CONFIG_USER_ONLY)
 170     env->uncached_cpsr = ARM_CPU_MODE_USR;
 171     /* For user mode we must enable access to coprocessors */
 172     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 173     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 174         env->cp15.c15_cpar = 3;
 175     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 176         env->cp15.c15_cpar = 1;
 177     }
 178 #else
 179     /* SVC mode with interrupts disabled.  */
 180     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 181     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 182
 183     if (arm_feature(env, ARM_FEATURE_M)) {
 184         uint32_t initial_msp; /* Loaded from 0x0 */
 185         uint32_t initial_pc; /* Loaded from 0x4 */
 186         uint8_t *rom;
 187
 188         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 189             env->v7m.secure = true;
 190         }
 191
 192         /* The reset value of this bit is IMPDEF, but ARM recommends
 193          * that it resets to 1, so QEMU always does that rather than making
 194          * it dependent on CPU model.
 195          */
 196         env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
 197
 198         /* Unlike A/R profile, M profile defines the reset LR value */
 199         env->regs[14] = 0xffffffff;
 200
 201         /* Load the initial SP and PC from the vector table at address 0 */
 202         rom = rom_ptr(0);
 203         if (rom) {
 204             /* Address zero is covered by ROM which hasn't yet been
 205              * copied into physical memory.
 206              */
 207             initial_msp = ldl_p(rom);
 208             initial_pc = ldl_p(rom + 4);
 209         } else {
 210             /* Address zero not covered by a ROM blob, or the ROM blob
 211              * is in non-modifiable memory and this is a second reset after
 212              * it got copied into memory. In the latter case, rom_ptr
 213              * will return a NULL pointer and we should use ldl_phys instead.
 214              */
 215             initial_msp = ldl_phys(s->as, 0);
 216             initial_pc = ldl_phys(s->as, 4);
 217         }
 218
 219         env->regs[13] = initial_msp & 0xFFFFFFFC;
 220         env->regs[15] = initial_pc & ~1;
 221         env->thumb = initial_pc & 1;
 222     }
 223
 224     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 225      * executing as AArch32 then check if highvecs are enabled and
 226      * adjust the PC accordingly.
 227      */
 228     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 229         env->regs[15] = 0xFFFF0000;
 230     }
 231
 232     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 233 #endif
 234
 235     if (arm_feature(env, ARM_FEATURE_PMSA)) {
 236         if (cpu->pmsav7_dregion > 0) {
 237             if (arm_feature(env, ARM_FEATURE_V8)) {
 238                 memset(env->pmsav8.rbar[M_REG_NS], 0,
 239                        sizeof(*env->pmsav8.rbar[M_REG_NS])
 240                        * cpu->pmsav7_dregion);
 241                 memset(env->pmsav8.rlar[M_REG_NS], 0,
 242                        sizeof(*env->pmsav8.rlar[M_REG_NS])
 243                        * cpu->pmsav7_dregion);
 244                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 245                     memset(env->pmsav8.rbar[M_REG_S], 0,
 246                            sizeof(*env->pmsav8.rbar[M_REG_S])
 247                            * cpu->pmsav7_dregion);
 248                     memset(env->pmsav8.rlar[M_REG_S], 0,
 249                            sizeof(*env->pmsav8.rlar[M_REG_S])
 250                            * cpu->pmsav7_dregion);
 251                 }
 252             } else if (arm_feature(env, ARM_FEATURE_V7)) {
 253                 memset(env->pmsav7.drbar, 0,
 254                        sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
 255                 memset(env->pmsav7.drsr, 0,
 256                        sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
 257                 memset(env->pmsav7.dracr, 0,
 258                        sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
 259             }
 260         }
 261         env->pmsav7.rnr = 0;
 262         env->pmsav8.mair0[M_REG_NS] = 0;
 263         env->pmsav8.mair0[M_REG_S] = 0;
 264         env->pmsav8.mair1[M_REG_NS] = 0;
 265         env->pmsav8.mair1[M_REG_S] = 0;
 266     }
 267
 268     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 269     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 270     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 271     set_float_detect_tininess(float_tininess_before_rounding,
 272                               &env->vfp.fp_status);
 273     set_float_detect_tininess(float_tininess_before_rounding,
 274                               &env->vfp.standard_fp_status);
 275 #ifndef CONFIG_USER_ONLY
 276     if (kvm_enabled()) {
 277         kvm_arm_reset_vcpu(cpu);
 278     }
 279 #endif
 280
 281     hw_breakpoint_update_all(cpu);
 282     hw_watchpoint_update_all(cpu);
 283 }
 284
 285 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 286 {
 287     CPUClass *cc = CPU_GET_CLASS(cs);
 288     CPUARMState *env = cs->env_ptr;
 289     uint32_t cur_el = arm_current_el(env);
 290     bool secure = arm_is_secure(env);
 291     uint32_t target_el;
 292     uint32_t excp_idx;
 293     bool ret = false;
 294
 295     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 296         excp_idx = EXCP_FIQ;
 297         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 298         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 299             cs->exception_index = excp_idx;
 300             env->exception.target_el = target_el;
 301             cc->do_interrupt(cs);
 302             ret = true;
 303         }
 304     }
 305     if (interrupt_request & CPU_INTERRUPT_HARD) {
 306         excp_idx = EXCP_IRQ;
 307         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 308         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 309             cs->exception_index = excp_idx;
 310             env->exception.target_el = target_el;
 311             cc->do_interrupt(cs);
 312             ret = true;
 313         }
 314     }
 315     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 316         excp_idx = EXCP_VIRQ;
 317         target_el = 1;
 318         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 319             cs->exception_index = excp_idx;
 320             env->exception.target_el = target_el;
 321             cc->do_interrupt(cs);
 322             ret = true;
 323         }
 324     }
 325     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 326         excp_idx = EXCP_VFIQ;
 327         target_el = 1;
 328         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 329             cs->exception_index = excp_idx;
 330             env->exception.target_el = target_el;
 331             cc->do_interrupt(cs);
 332             ret = true;
 333         }
 334     }
 335
 336     return ret;
 337 }
 338
 339 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 340 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 341 {
 342     CPUClass *cc = CPU_GET_CLASS(cs);
 343     ARMCPU *cpu = ARM_CPU(cs);
 344     CPUARMState *env = &cpu->env;
 345     bool ret = false;
 346
 347     /* ARMv7-M interrupt masking works differently than -A or -R.
 348      * There is no FIQ/IRQ distinction. Instead of I and F bits
 349      * masking FIQ and IRQ interrupts, an exception is taken only
 350      * if it is higher priority than the current execution priority
 351      * (which depends on state like BASEPRI, FAULTMASK and the
 352      * currently active exception).
 353      */
 354     if (interrupt_request & CPU_INTERRUPT_HARD
 355         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 356         cs->exception_index = EXCP_IRQ;
 357         cc->do_interrupt(cs);
 358         ret = true;
 359     }
 360     return ret;
 361 }
 362 #endif
 363
 364 #ifndef CONFIG_USER_ONLY
 365 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 366 {
 367     ARMCPU *cpu = opaque;
 368     CPUARMState *env = &cpu->env;
 369     CPUState *cs = CPU(cpu);
 370     static const int mask[] = {
 371         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 372         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 373         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 374         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 375     };
 376
 377     switch (irq) {
 378     case ARM_CPU_VIRQ:
 379     case ARM_CPU_VFIQ:
 380         assert(arm_feature(env, ARM_FEATURE_EL2));
 381         /* fall through */
 382     case ARM_CPU_IRQ:
 383     case ARM_CPU_FIQ:
 384         if (level) {
 385             cpu_interrupt(cs, mask[irq]);
 386         } else {
 387             cpu_reset_interrupt(cs, mask[irq]);
 388         }
 389         break;
 390     default:
 391         g_assert_not_reached();
 392     }
 393 }
 394
 395 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 396 {
 397 #ifdef CONFIG_KVM
 398     ARMCPU *cpu = opaque;
 399     CPUState *cs = CPU(cpu);
 400     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 401
 402     switch (irq) {
 403     case ARM_CPU_IRQ:
 404         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 405         break;
 406     case ARM_CPU_FIQ:
 407         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 408         break;
 409     default:
 410         g_assert_not_reached();
 411     }
 412     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 413     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 414 #endif
 415 }
 416
 417 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 418 {
 419     ARMCPU *cpu = ARM_CPU(cs);
 420     CPUARMState *env = &cpu->env;
 421
 422     cpu_synchronize_state(cs);
 423     return arm_cpu_data_is_big_endian(env);
 424 }
 425
 426 #endif
 427
 428 static inline void set_feature(CPUARMState *env, int feature)
 429 {
 430     env->features |= 1ULL << feature;
 431 }
 432
 433 static inline void unset_feature(CPUARMState *env, int feature)
 434 {
 435     env->features &= ~(1ULL << feature);
 436 }
 437
 438 static int
 439 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 440 {
 441   return print_insn_arm(pc | 1, info);
 442 }
 443
 444 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
 445                                 int length, struct disassemble_info *info)
 446 {
 447     assert(info->read_memory_inner_func);
 448     assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
 449
 450     if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
 451         assert(info->endian == BFD_ENDIAN_LITTLE);
 452         return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
 453                                             info);
 454     } else {
 455         return info->read_memory_inner_func(memaddr, b, length, info);
 456     }
 457 }
 458
 459 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 460 {
 461     ARMCPU *ac = ARM_CPU(cpu);
 462     CPUARMState *env = &ac->env;
 463
 464     if (is_a64(env)) {
 465         /* We might not be compiled with the A64 disassembler
 466          * because it needs a C++ compiler. Leave print_insn
 467          * unset in this case to use the caller default behaviour.
 468          */
 469 #if defined(CONFIG_ARM_A64_DIS)
 470         info->print_insn = print_insn_arm_a64;
 471 #endif
 472     } else if (env->thumb) {
 473         info->print_insn = print_insn_thumb1;
 474     } else {
 475         info->print_insn = print_insn_arm;
 476     }
 477     if (bswap_code(arm_sctlr_b(env))) {
 478 #ifdef TARGET_WORDS_BIGENDIAN
 479         info->endian = BFD_ENDIAN_LITTLE;
 480 #else
 481         info->endian = BFD_ENDIAN_BIG;
 482 #endif
 483     }
 484     if (info->read_memory_inner_func == NULL) {
 485         info->read_memory_inner_func = info->read_memory_func;
 486         info->read_memory_func = arm_read_memory_func;
 487     }
 488     info->flags &= ~INSN_ARM_BE32;
 489     if (arm_sctlr_b(env)) {
 490         info->flags |= INSN_ARM_BE32;
 491     }
 492 }
 493
 494 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
 495 {
 496     uint32_t Aff1 = idx / clustersz;
 497     uint32_t Aff0 = idx % clustersz;
 498     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 499 }
 500
 501 static void arm_cpu_initfn(Object *obj)
 502 {
 503     CPUState *cs = CPU(obj);
 504     ARMCPU *cpu = ARM_CPU(obj);
 505     static bool inited;
 506
 507     cs->env_ptr = &cpu->env;
 508     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 509                                          g_free, g_free);
 510
 511 #ifndef CONFIG_USER_ONLY
 512     /* Our inbound IRQ and FIQ lines */
 513     if (kvm_enabled()) {
 514         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 515          * the same interface as non-KVM CPUs.
 516          */
 517         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 518     } else {
 519         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 520     }
 521
 522     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 523                                                 arm_gt_ptimer_cb, cpu);
 524     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 525                                                 arm_gt_vtimer_cb, cpu);
 526     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 527                                                 arm_gt_htimer_cb, cpu);
 528     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 529                                                 arm_gt_stimer_cb, cpu);
 530     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 531                        ARRAY_SIZE(cpu->gt_timer_outputs));
 532
 533     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
 534                              "gicv3-maintenance-interrupt", 1);
 535     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
 536                              "pmu-interrupt", 1);
 537 #endif
 538
 539     /* DTB consumers generally don't in fact care what the 'compatible'
 540      * string is, so always provide some string and trust that a hypothetical
 541      * picky DTB consumer will also provide a helpful error message.
 542      */
 543     cpu->dtb_compatible = "qemu,unknown";
 544     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 545     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 546
 547     if (tcg_enabled()) {
 548         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 549         if (!inited) {
 550             inited = true;
 551             arm_translate_init();
 552         }
 553     }
 554 }
 555
 556 static Property arm_cpu_reset_cbar_property =
 557             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 558
 559 static Property arm_cpu_reset_hivecs_property =
 560             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 561
 562 static Property arm_cpu_rvbar_property =
 563             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 564
 565 static Property arm_cpu_has_el2_property =
 566             DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
 567
 568 static Property arm_cpu_has_el3_property =
 569             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 570
 571 static Property arm_cpu_cfgend_property =
 572             DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 573
 574 /* use property name "pmu" to match other archs and virt tools */
 575 static Property arm_cpu_has_pmu_property =
 576             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
 577
 578 static Property arm_cpu_has_mpu_property =
 579             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 580
 581 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
 582  * because the CPU initfn will have already set cpu->pmsav7_dregion to
 583  * the right value for that particular CPU type, and we don't want
 584  * to override that with an incorrect constant value.
 585  */
 586 static Property arm_cpu_pmsav7_dregion_property =
 587             DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
 588                                            pmsav7_dregion,
 589                                            qdev_prop_uint32, uint32_t);
 590
 591 static void arm_cpu_post_init(Object *obj)
 592 {
 593     ARMCPU *cpu = ARM_CPU(obj);
 594
 595     /* M profile implies PMSA. We have to do this here rather than
 596      * in realize with the other feature-implication checks because
 597      * we look at the PMSA bit to see if we should add some properties.
 598      */
 599     if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 600         set_feature(&cpu->env, ARM_FEATURE_PMSA);
 601     }
 602
 603     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 604         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 605         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 606                                  &error_abort);
 607     }
 608
 609     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 610         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 611                                  &error_abort);
 612     }
 613
 614     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 615         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 616                                  &error_abort);
 617     }
 618
 619     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 620         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 621          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 622          */
 623         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 624                                  &error_abort);
 625
 626 #ifndef CONFIG_USER_ONLY
 627         object_property_add_link(obj, "secure-memory",
 628                                  TYPE_MEMORY_REGION,
 629                                  (Object **)&cpu->secure_memory,
 630                                  qdev_prop_allow_set_link_before_realize,
 631                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 632                                  &error_abort);
 633 #endif
 634     }
 635
 636     if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
 637         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
 638                                  &error_abort);
 639     }
 640
 641     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
 642         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
 643                                  &error_abort);
 644     }
 645
 646     if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
 647         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 648                                  &error_abort);
 649         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 650             qdev_property_add_static(DEVICE(obj),
 651                                      &arm_cpu_pmsav7_dregion_property,
 652                                      &error_abort);
 653         }
 654     }
 655
 656     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
 657                              &error_abort);
 658 }
 659
 660 static void arm_cpu_finalizefn(Object *obj)
 661 {
 662     ARMCPU *cpu = ARM_CPU(obj);
 663     g_hash_table_destroy(cpu->cp_regs);
 664 }
 665
 666 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 667 {
 668     CPUState *cs = CPU(dev);
 669     ARMCPU *cpu = ARM_CPU(dev);
 670     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 671     CPUARMState *env = &cpu->env;
 672     int pagebits;
 673     Error *local_err = NULL;
 674
 675     cpu_exec_realizefn(cs, &local_err);
 676     if (local_err != NULL) {
 677         error_propagate(errp, local_err);
 678         return;
 679     }
 680
 681     /* Some features automatically imply others: */
 682     if (arm_feature(env, ARM_FEATURE_V8)) {
 683         set_feature(env, ARM_FEATURE_V7);
 684         set_feature(env, ARM_FEATURE_ARM_DIV);
 685         set_feature(env, ARM_FEATURE_LPAE);
 686     }
 687     if (arm_feature(env, ARM_FEATURE_V7)) {
 688         set_feature(env, ARM_FEATURE_VAPA);
 689         set_feature(env, ARM_FEATURE_THUMB2);
 690         set_feature(env, ARM_FEATURE_MPIDR);
 691         if (!arm_feature(env, ARM_FEATURE_M)) {
 692             set_feature(env, ARM_FEATURE_V6K);
 693         } else {
 694             set_feature(env, ARM_FEATURE_V6);
 695         }
 696
 697         /* Always define VBAR for V7 CPUs even if it doesn't exist in
 698          * non-EL3 configs. This is needed by some legacy boards.
 699          */
 700         set_feature(env, ARM_FEATURE_VBAR);
 701     }
 702     if (arm_feature(env, ARM_FEATURE_V6K)) {
 703         set_feature(env, ARM_FEATURE_V6);
 704         set_feature(env, ARM_FEATURE_MVFR);
 705     }
 706     if (arm_feature(env, ARM_FEATURE_V6)) {
 707         set_feature(env, ARM_FEATURE_V5);
 708         if (!arm_feature(env, ARM_FEATURE_M)) {
 709             set_feature(env, ARM_FEATURE_AUXCR);
 710         }
 711     }
 712     if (arm_feature(env, ARM_FEATURE_V5)) {
 713         set_feature(env, ARM_FEATURE_V4T);
 714     }
 715     if (arm_feature(env, ARM_FEATURE_M)) {
 716         set_feature(env, ARM_FEATURE_THUMB_DIV);
 717     }
 718     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 719         set_feature(env, ARM_FEATURE_THUMB_DIV);
 720     }
 721     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 722         set_feature(env, ARM_FEATURE_VFP3);
 723         set_feature(env, ARM_FEATURE_VFP_FP16);
 724     }
 725     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 726         set_feature(env, ARM_FEATURE_VFP);
 727     }
 728     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 729         set_feature(env, ARM_FEATURE_V7MP);
 730         set_feature(env, ARM_FEATURE_PXN);
 731     }
 732     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 733         set_feature(env, ARM_FEATURE_CBAR);
 734     }
 735     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 736         !arm_feature(env, ARM_FEATURE_M)) {
 737         set_feature(env, ARM_FEATURE_THUMB_DSP);
 738     }
 739
 740     if (arm_feature(env, ARM_FEATURE_V7) &&
 741         !arm_feature(env, ARM_FEATURE_M) &&
 742         !arm_feature(env, ARM_FEATURE_PMSA)) {
 743         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
 744          * can use 4K pages.
 745          */
 746         pagebits = 12;
 747     } else {
 748         /* For CPUs which might have tiny 1K pages, or which have an
 749          * MPU and might have small region sizes, stick with 1K pages.
 750          */
 751         pagebits = 10;
 752     }
 753     if (!set_preferred_target_page_bits(pagebits)) {
 754         /* This can only ever happen for hotplugging a CPU, or if
 755          * the board code incorrectly creates a CPU which it has
 756          * promised via minimum_page_size that it will not.
 757          */
 758         error_setg(errp, "This CPU requires a smaller page size than the "
 759                    "system is using");
 760         return;
 761     }
 762
 763     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 764      * We don't support setting cluster ID ([16..23]) (known as Aff2
 765      * in later ARM ARM versions), or any of the higher affinity level fields,
 766      * so these bits always RAZ.
 767      */
 768     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
 769         cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
 770                                                ARM_DEFAULT_CPUS_PER_CLUSTER);
 771     }
 772
 773     if (cpu->reset_hivecs) {
 774             cpu->reset_sctlr |= (1 << 13);
 775     }
 776
 777     if (cpu->cfgend) {
 778         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 779             cpu->reset_sctlr |= SCTLR_EE;
 780         } else {
 781             cpu->reset_sctlr |= SCTLR_B;
 782         }
 783     }
 784
 785     if (!cpu->has_el3) {
 786         /* If the has_el3 CPU property is disabled then we need to disable the
 787          * feature.
 788          */
 789         unset_feature(env, ARM_FEATURE_EL3);
 790
 791         /* Disable the security extension feature bits in the processor feature
 792          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 793          */
 794         cpu->id_pfr1 &= ~0xf0;
 795         cpu->id_aa64pfr0 &= ~0xf000;
 796     }
 797
 798     if (!cpu->has_el2) {
 799         unset_feature(env, ARM_FEATURE_EL2);
 800     }
 801
 802     if (!cpu->has_pmu) {
 803         unset_feature(env, ARM_FEATURE_PMU);
 804         cpu->id_aa64dfr0 &= ~0xf00;
 805     }
 806
 807     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 808         /* Disable the hypervisor feature bits in the processor feature
 809          * registers if we don't have EL2. These are id_pfr1[15:12] and
 810          * id_aa64pfr0_el1[11:8].
 811          */
 812         cpu->id_aa64pfr0 &= ~0xf00;
 813         cpu->id_pfr1 &= ~0xf000;
 814     }
 815
 816     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
 817      * to false or by setting pmsav7-dregion to 0.
 818      */
 819     if (!cpu->has_mpu) {
 820         cpu->pmsav7_dregion = 0;
 821     }
 822     if (cpu->pmsav7_dregion == 0) {
 823         cpu->has_mpu = false;
 824     }
 825
 826     if (arm_feature(env, ARM_FEATURE_PMSA) &&
 827         arm_feature(env, ARM_FEATURE_V7)) {
 828         uint32_t nr = cpu->pmsav7_dregion;
 829
 830         if (nr > 0xff) {
 831             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 832             return;
 833         }
 834
 835         if (nr) {
 836             if (arm_feature(env, ARM_FEATURE_V8)) {
 837                 /* PMSAv8 */
 838                 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
 839                 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
 840                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 841                     env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
 842                     env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
 843                 }
 844             } else {
 845                 env->pmsav7.drbar = g_new0(uint32_t, nr);
 846                 env->pmsav7.drsr = g_new0(uint32_t, nr);
 847                 env->pmsav7.dracr = g_new0(uint32_t, nr);
 848             }
 849         }
 850     }
 851
 852     if (arm_feature(env, ARM_FEATURE_EL3)) {
 853         set_feature(env, ARM_FEATURE_VBAR);
 854     }
 855
 856     register_cp_regs_for_features(cpu);
 857     arm_cpu_register_gdb_regs_for_features(cpu);
 858
 859     init_cpreg_list(cpu);
 860
 861 #ifndef CONFIG_USER_ONLY
 862     if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 863         AddressSpace *as;
 864
 865         cs->num_ases = 2;
 866
 867         if (!cpu->secure_memory) {
 868             cpu->secure_memory = cs->memory;
 869         }
 870         as = address_space_init_shareable(cpu->secure_memory,
 871                                           "cpu-secure-memory");
 872         cpu_address_space_init(cs, as, ARMASIdx_S);
 873     } else {
 874         cs->num_ases = 1;
 875     }
 876
 877     cpu_address_space_init(cs,
 878                            address_space_init_shareable(cs->memory,
 879                                                         "cpu-memory"),
 880                            ARMASIdx_NS);
 881 #endif
 882
 883     qemu_init_vcpu(cs);
 884     cpu_reset(cs);
 885
 886     acc->parent_realize(dev, errp);
 887 }
 888
 889 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 890 {
 891     ObjectClass *oc;
 892     char *typename;
 893     char **cpuname;
 894
 895     if (!cpu_model) {
 896         return NULL;
 897     }
 898
 899     cpuname = g_strsplit(cpu_model, ",", 1);
 900     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 901     oc = object_class_by_name(typename);
 902     g_strfreev(cpuname);
 903     g_free(typename);
 904     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 905         object_class_is_abstract(oc)) {
 906         return NULL;
 907     }
 908     return oc;
 909 }
 910
 911 /* CPU models. These are not needed for the AArch64 linux-user build. */
 912 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 913
 914 static void arm926_initfn(Object *obj)
 915 {
 916     ARMCPU *cpu = ARM_CPU(obj);
 917
 918     cpu->dtb_compatible = "arm,arm926";
 919     set_feature(&cpu->env, ARM_FEATURE_V5);
 920     set_feature(&cpu->env, ARM_FEATURE_VFP);
 921     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 922     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 923     cpu->midr = 0x41069265;
 924     cpu->reset_fpsid = 0x41011090;
 925     cpu->ctr = 0x1dd20d2;
 926     cpu->reset_sctlr = 0x00090078;
 927 }
 928
 929 static void arm946_initfn(Object *obj)
 930 {
 931     ARMCPU *cpu = ARM_CPU(obj);
 932
 933     cpu->dtb_compatible = "arm,arm946";
 934     set_feature(&cpu->env, ARM_FEATURE_V5);
 935     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 936     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 937     cpu->midr = 0x41059461;
 938     cpu->ctr = 0x0f004006;
 939     cpu->reset_sctlr = 0x00000078;
 940 }
 941
 942 static void arm1026_initfn(Object *obj)
 943 {
 944     ARMCPU *cpu = ARM_CPU(obj);
 945
 946     cpu->dtb_compatible = "arm,arm1026";
 947     set_feature(&cpu->env, ARM_FEATURE_V5);
 948     set_feature(&cpu->env, ARM_FEATURE_VFP);
 949     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 950     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 951     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 952     cpu->midr = 0x4106a262;
 953     cpu->reset_fpsid = 0x410110a0;
 954     cpu->ctr = 0x1dd20d2;
 955     cpu->reset_sctlr = 0x00090078;
 956     cpu->reset_auxcr = 1;
 957     {
 958         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 959         ARMCPRegInfo ifar = {
 960             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 961             .access = PL1_RW,
 962             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 963             .resetvalue = 0
 964         };
 965         define_one_arm_cp_reg(cpu, &ifar);
 966     }
 967 }
 968
 969 static void arm1136_r2_initfn(Object *obj)
 970 {
 971     ARMCPU *cpu = ARM_CPU(obj);
 972     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 973      * older core than plain "arm1136". In particular this does not
 974      * have the v6K features.
 975      * These ID register values are correct for 1136 but may be wrong
 976      * for 1136_r2 (in particular r0p2 does not actually implement most
 977      * of the ID registers).
 978      */
 979
 980     cpu->dtb_compatible = "arm,arm1136";
 981     set_feature(&cpu->env, ARM_FEATURE_V6);
 982     set_feature(&cpu->env, ARM_FEATURE_VFP);
 983     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 984     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 985     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 986     cpu->midr = 0x4107b362;
 987     cpu->reset_fpsid = 0x410120b4;
 988     cpu->mvfr0 = 0x11111111;
 989     cpu->mvfr1 = 0x00000000;
 990     cpu->ctr = 0x1dd20d2;
 991     cpu->reset_sctlr = 0x00050078;
 992     cpu->id_pfr0 = 0x111;
 993     cpu->id_pfr1 = 0x1;
 994     cpu->id_dfr0 = 0x2;
 995     cpu->id_afr0 = 0x3;
 996     cpu->id_mmfr0 = 0x01130003;
 997     cpu->id_mmfr1 = 0x10030302;
 998     cpu->id_mmfr2 = 0x01222110;
 999     cpu->id_isar0 = 0x00140011;
1000     cpu->id_isar1 = 0x12002111;
1001     cpu->id_isar2 = 0x11231111;
1002     cpu->id_isar3 = 0x01102131;
1003     cpu->id_isar4 = 0x141;
1004     cpu->reset_auxcr = 7;
1005 }
1006
1007 static void arm1136_initfn(Object *obj)
1008 {
1009     ARMCPU *cpu = ARM_CPU(obj);
1010
1011     cpu->dtb_compatible = "arm,arm1136";
1012     set_feature(&cpu->env, ARM_FEATURE_V6K);
1013     set_feature(&cpu->env, ARM_FEATURE_V6);
1014     set_feature(&cpu->env, ARM_FEATURE_VFP);
1015     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1016     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1017     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1018     cpu->midr = 0x4117b363;
1019     cpu->reset_fpsid = 0x410120b4;
1020     cpu->mvfr0 = 0x11111111;
1021     cpu->mvfr1 = 0x00000000;
1022     cpu->ctr = 0x1dd20d2;
1023     cpu->reset_sctlr = 0x00050078;
1024     cpu->id_pfr0 = 0x111;
1025     cpu->id_pfr1 = 0x1;
1026     cpu->id_dfr0 = 0x2;
1027     cpu->id_afr0 = 0x3;
1028     cpu->id_mmfr0 = 0x01130003;
1029     cpu->id_mmfr1 = 0x10030302;
1030     cpu->id_mmfr2 = 0x01222110;
1031     cpu->id_isar0 = 0x00140011;
1032     cpu->id_isar1 = 0x12002111;
1033     cpu->id_isar2 = 0x11231111;
1034     cpu->id_isar3 = 0x01102131;
1035     cpu->id_isar4 = 0x141;
1036     cpu->reset_auxcr = 7;
1037 }
1038
1039 static void arm1176_initfn(Object *obj)
1040 {
1041     ARMCPU *cpu = ARM_CPU(obj);
1042
1043     cpu->dtb_compatible = "arm,arm1176";
1044     set_feature(&cpu->env, ARM_FEATURE_V6K);
1045     set_feature(&cpu->env, ARM_FEATURE_VFP);
1046     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1047     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1048     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1049     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1050     set_feature(&cpu->env, ARM_FEATURE_EL3);
1051     cpu->midr = 0x410fb767;
1052     cpu->reset_fpsid = 0x410120b5;
1053     cpu->mvfr0 = 0x11111111;
1054     cpu->mvfr1 = 0x00000000;
1055     cpu->ctr = 0x1dd20d2;
1056     cpu->reset_sctlr = 0x00050078;
1057     cpu->id_pfr0 = 0x111;
1058     cpu->id_pfr1 = 0x11;
1059     cpu->id_dfr0 = 0x33;
1060     cpu->id_afr0 = 0;
1061     cpu->id_mmfr0 = 0x01130003;
1062     cpu->id_mmfr1 = 0x10030302;
1063     cpu->id_mmfr2 = 0x01222100;
1064     cpu->id_isar0 = 0x0140011;
1065     cpu->id_isar1 = 0x12002111;
1066     cpu->id_isar2 = 0x11231121;
1067     cpu->id_isar3 = 0x01102131;
1068     cpu->id_isar4 = 0x01141;
1069     cpu->reset_auxcr = 7;
1070 }
1071
1072 static void arm11mpcore_initfn(Object *obj)
1073 {
1074     ARMCPU *cpu = ARM_CPU(obj);
1075
1076     cpu->dtb_compatible = "arm,arm11mpcore";
1077     set_feature(&cpu->env, ARM_FEATURE_V6K);
1078     set_feature(&cpu->env, ARM_FEATURE_VFP);
1079     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1080     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1081     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1082     cpu->midr = 0x410fb022;
1083     cpu->reset_fpsid = 0x410120b4;
1084     cpu->mvfr0 = 0x11111111;
1085     cpu->mvfr1 = 0x00000000;
1086     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1087     cpu->id_pfr0 = 0x111;
1088     cpu->id_pfr1 = 0x1;
1089     cpu->id_dfr0 = 0;
1090     cpu->id_afr0 = 0x2;
1091     cpu->id_mmfr0 = 0x01100103;
1092     cpu->id_mmfr1 = 0x10020302;
1093     cpu->id_mmfr2 = 0x01222000;
1094     cpu->id_isar0 = 0x00100011;
1095     cpu->id_isar1 = 0x12002111;
1096     cpu->id_isar2 = 0x11221011;
1097     cpu->id_isar3 = 0x01102131;
1098     cpu->id_isar4 = 0x141;
1099     cpu->reset_auxcr = 1;
1100 }
1101
1102 static void cortex_m3_initfn(Object *obj)
1103 {
1104     ARMCPU *cpu = ARM_CPU(obj);
1105     set_feature(&cpu->env, ARM_FEATURE_V7);
1106     set_feature(&cpu->env, ARM_FEATURE_M);
1107     cpu->midr = 0x410fc231;
1108     cpu->pmsav7_dregion = 8;
1109 }
1110
1111 static void cortex_m4_initfn(Object *obj)
1112 {
1113     ARMCPU *cpu = ARM_CPU(obj);
1114
1115     set_feature(&cpu->env, ARM_FEATURE_V7);
1116     set_feature(&cpu->env, ARM_FEATURE_M);
1117     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1118     cpu->midr = 0x410fc240; /* r0p0 */
1119     cpu->pmsav7_dregion = 8;
1120 }
1121 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1122 {
1123     CPUClass *cc = CPU_CLASS(oc);
1124
1125 #ifndef CONFIG_USER_ONLY
1126     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1127 #endif
1128
1129     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1130 }
1131
1132 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1133     /* Dummy the TCM region regs for the moment */
1134     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1135       .access = PL1_RW, .type = ARM_CP_CONST },
1136     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1137       .access = PL1_RW, .type = ARM_CP_CONST },
1138     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1139       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1140     REGINFO_SENTINEL
1141 };
1142
1143 static void cortex_r5_initfn(Object *obj)
1144 {
1145     ARMCPU *cpu = ARM_CPU(obj);
1146
1147     set_feature(&cpu->env, ARM_FEATURE_V7);
1148     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1149     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1150     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1151     set_feature(&cpu->env, ARM_FEATURE_PMSA);
1152     cpu->midr = 0x411fc153; /* r1p3 */
1153     cpu->id_pfr0 = 0x0131;
1154     cpu->id_pfr1 = 0x001;
1155     cpu->id_dfr0 = 0x010400;
1156     cpu->id_afr0 = 0x0;
1157     cpu->id_mmfr0 = 0x0210030;
1158     cpu->id_mmfr1 = 0x00000000;
1159     cpu->id_mmfr2 = 0x01200000;
1160     cpu->id_mmfr3 = 0x0211;
1161     cpu->id_isar0 = 0x2101111;
1162     cpu->id_isar1 = 0x13112111;
1163     cpu->id_isar2 = 0x21232141;
1164     cpu->id_isar3 = 0x01112131;
1165     cpu->id_isar4 = 0x0010142;
1166     cpu->id_isar5 = 0x0;
1167     cpu->mp_is_up = true;
1168     cpu->pmsav7_dregion = 16;
1169     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1170 }
1171
1172 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1173     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1174       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1175     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1176       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1177     REGINFO_SENTINEL
1178 };
1179
1180 static void cortex_a8_initfn(Object *obj)
1181 {
1182     ARMCPU *cpu = ARM_CPU(obj);
1183
1184     cpu->dtb_compatible = "arm,cortex-a8";
1185     set_feature(&cpu->env, ARM_FEATURE_V7);
1186     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1187     set_feature(&cpu->env, ARM_FEATURE_NEON);
1188     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1189     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1190     set_feature(&cpu->env, ARM_FEATURE_EL3);
1191     cpu->midr = 0x410fc080;
1192     cpu->reset_fpsid = 0x410330c0;
1193     cpu->mvfr0 = 0x11110222;
1194     cpu->mvfr1 = 0x00011111;
1195     cpu->ctr = 0x82048004;
1196     cpu->reset_sctlr = 0x00c50078;
1197     cpu->id_pfr0 = 0x1031;
1198     cpu->id_pfr1 = 0x11;
1199     cpu->id_dfr0 = 0x400;
1200     cpu->id_afr0 = 0;
1201     cpu->id_mmfr0 = 0x31100003;
1202     cpu->id_mmfr1 = 0x20000000;
1203     cpu->id_mmfr2 = 0x01202000;
1204     cpu->id_mmfr3 = 0x11;
1205     cpu->id_isar0 = 0x00101111;
1206     cpu->id_isar1 = 0x12112111;
1207     cpu->id_isar2 = 0x21232031;
1208     cpu->id_isar3 = 0x11112131;
1209     cpu->id_isar4 = 0x00111142;
1210     cpu->dbgdidr = 0x15141000;
1211     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1212     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1213     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1214     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1215     cpu->reset_auxcr = 2;
1216     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1217 }
1218
1219 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1220     /* power_control should be set to maximum latency. Again,
1221      * default to 0 and set by private hook
1222      */
1223     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1224       .access = PL1_RW, .resetvalue = 0,
1225       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1226     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1227       .access = PL1_RW, .resetvalue = 0,
1228       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1229     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1230       .access = PL1_RW, .resetvalue = 0,
1231       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1232     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1233       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1234     /* TLB lockdown control */
1235     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1236       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1237     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1238       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1239     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1240       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1241     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1242       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1243     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1244       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1245     REGINFO_SENTINEL
1246 };
1247
1248 static void cortex_a9_initfn(Object *obj)
1249 {
1250     ARMCPU *cpu = ARM_CPU(obj);
1251
1252     cpu->dtb_compatible = "arm,cortex-a9";
1253     set_feature(&cpu->env, ARM_FEATURE_V7);
1254     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1255     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1256     set_feature(&cpu->env, ARM_FEATURE_NEON);
1257     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1258     set_feature(&cpu->env, ARM_FEATURE_EL3);
1259     /* Note that A9 supports the MP extensions even for
1260      * A9UP and single-core A9MP (which are both different
1261      * and valid configurations; we don't model A9UP).
1262      */
1263     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1264     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1265     cpu->midr = 0x410fc090;
1266     cpu->reset_fpsid = 0x41033090;
1267     cpu->mvfr0 = 0x11110222;
1268     cpu->mvfr1 = 0x01111111;
1269     cpu->ctr = 0x80038003;
1270     cpu->reset_sctlr = 0x00c50078;
1271     cpu->id_pfr0 = 0x1031;
1272     cpu->id_pfr1 = 0x11;
1273     cpu->id_dfr0 = 0x000;
1274     cpu->id_afr0 = 0;
1275     cpu->id_mmfr0 = 0x00100103;
1276     cpu->id_mmfr1 = 0x20000000;
1277     cpu->id_mmfr2 = 0x01230000;
1278     cpu->id_mmfr3 = 0x00002111;
1279     cpu->id_isar0 = 0x00101111;
1280     cpu->id_isar1 = 0x13112111;
1281     cpu->id_isar2 = 0x21232041;
1282     cpu->id_isar3 = 0x11112131;
1283     cpu->id_isar4 = 0x00111142;
1284     cpu->dbgdidr = 0x35141000;
1285     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1286     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1287     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1288     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1289 }
1290
1291 #ifndef CONFIG_USER_ONLY
1292 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1293 {
1294     /* Linux wants the number of processors from here.
1295      * Might as well set the interrupt-controller bit too.
1296      */
1297     return ((smp_cpus - 1) << 24) | (1 << 23);
1298 }
1299 #endif
1300
1301 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1302 #ifndef CONFIG_USER_ONLY
1303     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1304       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1305       .writefn = arm_cp_write_ignore, },
1306 #endif
1307     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1308       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1309     REGINFO_SENTINEL
1310 };
1311
1312 static void cortex_a7_initfn(Object *obj)
1313 {
1314     ARMCPU *cpu = ARM_CPU(obj);
1315
1316     cpu->dtb_compatible = "arm,cortex-a7";
1317     set_feature(&cpu->env, ARM_FEATURE_V7);
1318     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1319     set_feature(&cpu->env, ARM_FEATURE_NEON);
1320     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1321     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1322     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1323     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1324     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1325     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1326     set_feature(&cpu->env, ARM_FEATURE_EL3);
1327     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1328     cpu->midr = 0x410fc075;
1329     cpu->reset_fpsid = 0x41023075;
1330     cpu->mvfr0 = 0x10110222;
1331     cpu->mvfr1 = 0x11111111;
1332     cpu->ctr = 0x84448003;
1333     cpu->reset_sctlr = 0x00c50078;
1334     cpu->id_pfr0 = 0x00001131;
1335     cpu->id_pfr1 = 0x00011011;
1336     cpu->id_dfr0 = 0x02010555;
1337     cpu->pmceid0 = 0x00000000;
1338     cpu->pmceid1 = 0x00000000;
1339     cpu->id_afr0 = 0x00000000;
1340     cpu->id_mmfr0 = 0x10101105;
1341     cpu->id_mmfr1 = 0x40000000;
1342     cpu->id_mmfr2 = 0x01240000;
1343     cpu->id_mmfr3 = 0x02102211;
1344     cpu->id_isar0 = 0x01101110;
1345     cpu->id_isar1 = 0x13112111;
1346     cpu->id_isar2 = 0x21232041;
1347     cpu->id_isar3 = 0x11112131;
1348     cpu->id_isar4 = 0x10011142;
1349     cpu->dbgdidr = 0x3515f005;
1350     cpu->clidr = 0x0a200023;
1351     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1352     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1353     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1354     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1355 }
1356
1357 static void cortex_a15_initfn(Object *obj)
1358 {
1359     ARMCPU *cpu = ARM_CPU(obj);
1360
1361     cpu->dtb_compatible = "arm,cortex-a15";
1362     set_feature(&cpu->env, ARM_FEATURE_V7);
1363     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1364     set_feature(&cpu->env, ARM_FEATURE_NEON);
1365     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1366     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1367     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1368     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1369     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1370     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1371     set_feature(&cpu->env, ARM_FEATURE_EL3);
1372     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1373     cpu->midr = 0x412fc0f1;
1374     cpu->reset_fpsid = 0x410430f0;
1375     cpu->mvfr0 = 0x10110222;
1376     cpu->mvfr1 = 0x11111111;
1377     cpu->ctr = 0x8444c004;
1378     cpu->reset_sctlr = 0x00c50078;
1379     cpu->id_pfr0 = 0x00001131;
1380     cpu->id_pfr1 = 0x00011011;
1381     cpu->id_dfr0 = 0x02010555;
1382     cpu->pmceid0 = 0x0000000;
1383     cpu->pmceid1 = 0x00000000;
1384     cpu->id_afr0 = 0x00000000;
1385     cpu->id_mmfr0 = 0x10201105;
1386     cpu->id_mmfr1 = 0x20000000;
1387     cpu->id_mmfr2 = 0x01240000;
1388     cpu->id_mmfr3 = 0x02102211;
1389     cpu->id_isar0 = 0x02101110;
1390     cpu->id_isar1 = 0x13112111;
1391     cpu->id_isar2 = 0x21232041;
1392     cpu->id_isar3 = 0x11112131;
1393     cpu->id_isar4 = 0x10011142;
1394     cpu->dbgdidr = 0x3515f021;
1395     cpu->clidr = 0x0a200023;
1396     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1397     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1398     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1399     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1400 }
1401
1402 static void ti925t_initfn(Object *obj)
1403 {
1404     ARMCPU *cpu = ARM_CPU(obj);
1405     set_feature(&cpu->env, ARM_FEATURE_V4T);
1406     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1407     cpu->midr = ARM_CPUID_TI925T;
1408     cpu->ctr = 0x5109149;
1409     cpu->reset_sctlr = 0x00000070;
1410 }
1411
1412 static void sa1100_initfn(Object *obj)
1413 {
1414     ARMCPU *cpu = ARM_CPU(obj);
1415
1416     cpu->dtb_compatible = "intel,sa1100";
1417     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1418     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1419     cpu->midr = 0x4401A11B;
1420     cpu->reset_sctlr = 0x00000070;
1421 }
1422
1423 static void sa1110_initfn(Object *obj)
1424 {
1425     ARMCPU *cpu = ARM_CPU(obj);
1426     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1427     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1428     cpu->midr = 0x6901B119;
1429     cpu->reset_sctlr = 0x00000070;
1430 }
1431
1432 static void pxa250_initfn(Object *obj)
1433 {
1434     ARMCPU *cpu = ARM_CPU(obj);
1435
1436     cpu->dtb_compatible = "marvell,xscale";
1437     set_feature(&cpu->env, ARM_FEATURE_V5);
1438     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1439     cpu->midr = 0x69052100;
1440     cpu->ctr = 0xd172172;
1441     cpu->reset_sctlr = 0x00000078;
1442 }
1443
1444 static void pxa255_initfn(Object *obj)
1445 {
1446     ARMCPU *cpu = ARM_CPU(obj);
1447
1448     cpu->dtb_compatible = "marvell,xscale";
1449     set_feature(&cpu->env, ARM_FEATURE_V5);
1450     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1451     cpu->midr = 0x69052d00;
1452     cpu->ctr = 0xd172172;
1453     cpu->reset_sctlr = 0x00000078;
1454 }
1455
1456 static void pxa260_initfn(Object *obj)
1457 {
1458     ARMCPU *cpu = ARM_CPU(obj);
1459
1460     cpu->dtb_compatible = "marvell,xscale";
1461     set_feature(&cpu->env, ARM_FEATURE_V5);
1462     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1463     cpu->midr = 0x69052903;
1464     cpu->ctr = 0xd172172;
1465     cpu->reset_sctlr = 0x00000078;
1466 }
1467
1468 static void pxa261_initfn(Object *obj)
1469 {
1470     ARMCPU *cpu = ARM_CPU(obj);
1471
1472     cpu->dtb_compatible = "marvell,xscale";
1473     set_feature(&cpu->env, ARM_FEATURE_V5);
1474     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1475     cpu->midr = 0x69052d05;
1476     cpu->ctr = 0xd172172;
1477     cpu->reset_sctlr = 0x00000078;
1478 }
1479
1480 static void pxa262_initfn(Object *obj)
1481 {
1482     ARMCPU *cpu = ARM_CPU(obj);
1483
1484     cpu->dtb_compatible = "marvell,xscale";
1485     set_feature(&cpu->env, ARM_FEATURE_V5);
1486     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1487     cpu->midr = 0x69052d06;
1488     cpu->ctr = 0xd172172;
1489     cpu->reset_sctlr = 0x00000078;
1490 }
1491
1492 static void pxa270a0_initfn(Object *obj)
1493 {
1494     ARMCPU *cpu = ARM_CPU(obj);
1495
1496     cpu->dtb_compatible = "marvell,xscale";
1497     set_feature(&cpu->env, ARM_FEATURE_V5);
1498     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1499     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1500     cpu->midr = 0x69054110;
1501     cpu->ctr = 0xd172172;
1502     cpu->reset_sctlr = 0x00000078;
1503 }
1504
1505 static void pxa270a1_initfn(Object *obj)
1506 {
1507     ARMCPU *cpu = ARM_CPU(obj);
1508
1509     cpu->dtb_compatible = "marvell,xscale";
1510     set_feature(&cpu->env, ARM_FEATURE_V5);
1511     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1512     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1513     cpu->midr = 0x69054111;
1514     cpu->ctr = 0xd172172;
1515     cpu->reset_sctlr = 0x00000078;
1516 }
1517
1518 static void pxa270b0_initfn(Object *obj)
1519 {
1520     ARMCPU *cpu = ARM_CPU(obj);
1521
1522     cpu->dtb_compatible = "marvell,xscale";
1523     set_feature(&cpu->env, ARM_FEATURE_V5);
1524     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1525     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1526     cpu->midr = 0x69054112;
1527     cpu->ctr = 0xd172172;
1528     cpu->reset_sctlr = 0x00000078;
1529 }
1530
1531 static void pxa270b1_initfn(Object *obj)
1532 {
1533     ARMCPU *cpu = ARM_CPU(obj);
1534
1535     cpu->dtb_compatible = "marvell,xscale";
1536     set_feature(&cpu->env, ARM_FEATURE_V5);
1537     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1538     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1539     cpu->midr = 0x69054113;
1540     cpu->ctr = 0xd172172;
1541     cpu->reset_sctlr = 0x00000078;
1542 }
1543
1544 static void pxa270c0_initfn(Object *obj)
1545 {
1546     ARMCPU *cpu = ARM_CPU(obj);
1547
1548     cpu->dtb_compatible = "marvell,xscale";
1549     set_feature(&cpu->env, ARM_FEATURE_V5);
1550     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1551     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1552     cpu->midr = 0x69054114;
1553     cpu->ctr = 0xd172172;
1554     cpu->reset_sctlr = 0x00000078;
1555 }
1556
1557 static void pxa270c5_initfn(Object *obj)
1558 {
1559     ARMCPU *cpu = ARM_CPU(obj);
1560
1561     cpu->dtb_compatible = "marvell,xscale";
1562     set_feature(&cpu->env, ARM_FEATURE_V5);
1563     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1564     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1565     cpu->midr = 0x69054117;
1566     cpu->ctr = 0xd172172;
1567     cpu->reset_sctlr = 0x00000078;
1568 }
1569
1570 #ifdef CONFIG_USER_ONLY
1571 static void arm_any_initfn(Object *obj)
1572 {
1573     ARMCPU *cpu = ARM_CPU(obj);
1574     set_feature(&cpu->env, ARM_FEATURE_V8);
1575     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1576     set_feature(&cpu->env, ARM_FEATURE_NEON);
1577     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1578     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1579     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1580     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1581     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1582     set_feature(&cpu->env, ARM_FEATURE_CRC);
1583     cpu->midr = 0xffffffff;
1584 }
1585 #endif
1586
1587 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1588
1589 typedef struct ARMCPUInfo {
1590     const char *name;
1591     void (*initfn)(Object *obj);
1592     void (*class_init)(ObjectClass *oc, void *data);
1593 } ARMCPUInfo;
1594
1595 static const ARMCPUInfo arm_cpus[] = {
1596 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1597     { .name = "arm926",      .initfn = arm926_initfn },
1598     { .name = "arm946",      .initfn = arm946_initfn },
1599     { .name = "arm1026",     .initfn = arm1026_initfn },
1600     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1601      * older core than plain "arm1136". In particular this does not
1602      * have the v6K features.
1603      */
1604     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1605     { .name = "arm1136",     .initfn = arm1136_initfn },
1606     { .name = "arm1176",     .initfn = arm1176_initfn },
1607     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1608     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1609                              .class_init = arm_v7m_class_init },
1610     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1611                              .class_init = arm_v7m_class_init },
1612     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1613     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1614     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1615     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1616     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1617     { .name = "ti925t",      .initfn = ti925t_initfn },
1618     { .name = "sa1100",      .initfn = sa1100_initfn },
1619     { .name = "sa1110",      .initfn = sa1110_initfn },
1620     { .name = "pxa250",      .initfn = pxa250_initfn },
1621     { .name = "pxa255",      .initfn = pxa255_initfn },
1622     { .name = "pxa260",      .initfn = pxa260_initfn },
1623     { .name = "pxa261",      .initfn = pxa261_initfn },
1624     { .name = "pxa262",      .initfn = pxa262_initfn },
1625     /* "pxa270" is an alias for "pxa270-a0" */
1626     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1627     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1628     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1629     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1630     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1631     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1632     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1633 #ifdef CONFIG_USER_ONLY
1634     { .name = "any",         .initfn = arm_any_initfn },
1635 #endif
1636 #endif
1637     { .name = NULL }
1638 };
1639
1640 static Property arm_cpu_properties[] = {
1641     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1642     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1643     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1644     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1645                         mp_affinity, ARM64_AFFINITY_INVALID),
1646     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
1647     DEFINE_PROP_END_OF_LIST()
1648 };
1649
1650 #ifdef CONFIG_USER_ONLY
1651 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1652                                     int mmu_idx)
1653 {
1654     ARMCPU *cpu = ARM_CPU(cs);
1655     CPUARMState *env = &cpu->env;
1656
1657     env->exception.vaddress = address;
1658     if (rw == 2) {
1659         cs->exception_index = EXCP_PREFETCH_ABORT;
1660     } else {
1661         cs->exception_index = EXCP_DATA_ABORT;
1662     }
1663     return 1;
1664 }
1665 #endif
1666
1667 static gchar *arm_gdb_arch_name(CPUState *cs)
1668 {
1669     ARMCPU *cpu = ARM_CPU(cs);
1670     CPUARMState *env = &cpu->env;
1671
1672     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1673         return g_strdup("iwmmxt");
1674     }
1675     return g_strdup("arm");
1676 }
1677
1678 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1679 {
1680     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1681     CPUClass *cc = CPU_CLASS(acc);
1682     DeviceClass *dc = DEVICE_CLASS(oc);
1683
1684     acc->parent_realize = dc->realize;
1685     dc->realize = arm_cpu_realizefn;
1686     dc->props = arm_cpu_properties;
1687
1688     acc->parent_reset = cc->reset;
1689     cc->reset = arm_cpu_reset;
1690
1691     cc->class_by_name = arm_cpu_class_by_name;
1692     cc->has_work = arm_cpu_has_work;
1693     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1694     cc->dump_state = arm_cpu_dump_state;
1695     cc->set_pc = arm_cpu_set_pc;
1696     cc->gdb_read_register = arm_cpu_gdb_read_register;
1697     cc->gdb_write_register = arm_cpu_gdb_write_register;
1698 #ifdef CONFIG_USER_ONLY
1699     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1700 #else
1701     cc->do_interrupt = arm_cpu_do_interrupt;
1702     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1703     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1704     cc->asidx_from_attrs = arm_asidx_from_attrs;
1705     cc->vmsd = &vmstate_arm_cpu;
1706     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1707     cc->write_elf64_note = arm_cpu_write_elf64_note;
1708     cc->write_elf32_note = arm_cpu_write_elf32_note;
1709 #endif
1710     cc->gdb_num_core_regs = 26;
1711     cc->gdb_core_xml_file = "arm-core.xml";
1712     cc->gdb_arch_name = arm_gdb_arch_name;
1713     cc->gdb_stop_before_watchpoint = true;
1714     cc->debug_excp_handler = arm_debug_excp_handler;
1715     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1716 #if !defined(CONFIG_USER_ONLY)
1717     cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
1718 #endif
1719
1720     cc->disas_set_info = arm_disas_set_info;
1721 }
1722
1723 static void cpu_register(const ARMCPUInfo *info)
1724 {
1725     TypeInfo type_info = {
1726         .parent = TYPE_ARM_CPU,
1727         .instance_size = sizeof(ARMCPU),
1728         .instance_init = info->initfn,
1729         .class_size = sizeof(ARMCPUClass),
1730         .class_init = info->class_init,
1731     };
1732
1733     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1734     type_register(&type_info);
1735     g_free((void *)type_info.name);
1736 }
1737
1738 static const TypeInfo arm_cpu_type_info = {
1739     .name = TYPE_ARM_CPU,
1740     .parent = TYPE_CPU,
1741     .instance_size = sizeof(ARMCPU),
1742     .instance_init = arm_cpu_initfn,
1743     .instance_post_init = arm_cpu_post_init,
1744     .instance_finalize = arm_cpu_finalizefn,
1745     .abstract = true,
1746     .class_size = sizeof(ARMCPUClass),
1747     .class_init = arm_cpu_class_init,
1748 };
1749
1750 static void arm_cpu_register_types(void)
1751 {
1752     const ARMCPUInfo *info = arm_cpus;
1753
1754     type_register_static(&arm_cpu_type_info);
1755
1756     while (info->name) {
1757         cpu_register(info);
1758         info++;
1759     }
1760 }
1761
1762 type_init(arm_cpu_register_types)