4 #include "sysemu/dma.h"
6 #include "hw/ppc/xics.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
14 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
15 typedef struct sPAPREventSource sPAPREventSource;
16 typedef struct sPAPRPendingHPT sPAPRPendingHPT;
18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
19 #define SPAPR_ENTRY_POINT 0x100
21 #define SPAPR_TIMEBASE_FREQ 512000000ULL
23 #define TYPE_SPAPR_RTC "spapr-rtc"
25 #define SPAPR_RTC(obj) \
26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
28 typedef struct sPAPRRTCState sPAPRRTCState;
29 struct sPAPRRTCState {
31 DeviceState parent_obj;
35 typedef struct sPAPRDIMMState sPAPRDIMMState;
36 typedef struct sPAPRMachineClass sPAPRMachineClass;
38 #define TYPE_SPAPR_MACHINE "spapr-machine"
39 #define SPAPR_MACHINE(obj) \
40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
41 #define SPAPR_MACHINE_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
43 #define SPAPR_MACHINE_CLASS(klass) \
44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
47 SPAPR_RESIZE_HPT_DEFAULT = 0,
48 SPAPR_RESIZE_HPT_DISABLED,
49 SPAPR_RESIZE_HPT_ENABLED,
50 SPAPR_RESIZE_HPT_REQUIRED,
57 /* Hardware Transactional Memory */
58 #define SPAPR_CAP_HTM 0x00
59 /* Vector Scalar Extensions */
60 #define SPAPR_CAP_VSX 0x01
61 /* Decimal Floating Point */
62 #define SPAPR_CAP_DFP 0x02
63 /* Cache Flush on Privilege Change */
64 #define SPAPR_CAP_CFPC 0x03
65 /* Speculation Barrier Bounds Checking */
66 #define SPAPR_CAP_SBBC 0x04
68 #define SPAPR_CAP_NUM (SPAPR_CAP_SBBC + 1)
74 #define SPAPR_CAP_OFF 0x00
75 #define SPAPR_CAP_ON 0x01
76 /* Broken | Workaround | Fixed Caps */
77 #define SPAPR_CAP_BROKEN 0x00
78 #define SPAPR_CAP_WORKAROUND 0x01
79 #define SPAPR_CAP_FIXED 0x02
81 typedef struct sPAPRCapabilities sPAPRCapabilities;
82 struct sPAPRCapabilities {
83 uint8_t caps[SPAPR_CAP_NUM];
89 struct sPAPRMachineClass {
91 MachineClass parent_class;
94 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
95 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
96 bool pre_2_10_has_unused_icps;
97 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
98 uint64_t *buid, hwaddr *pio,
99 hwaddr *mmio32, hwaddr *mmio64,
100 unsigned n_dma, uint32_t *liobns, Error **errp);
101 sPAPRResizeHPT resize_hpt_default;
102 sPAPRCapabilities default_caps;
108 struct sPAPRMachineState {
110 MachineState parent_obj;
112 struct VIOsPAPRBus *vio_bus;
113 QLIST_HEAD(, sPAPRPHBState) phbs;
114 struct sPAPRNVRAM *nvram;
118 sPAPRResizeHPT resize_hpt;
121 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
122 sPAPRPendingHPT *pending_hpt; /* in-progress resize */
130 uint32_t initrd_base;
132 uint64_t rtc_offset; /* Now used only during incoming migration */
133 struct PPCTimebase tb;
135 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
137 Notifier epow_notifier;
138 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
139 bool use_hotplug_event_source;
140 sPAPREventSource *event_sources;
142 /* ibm,client-architecture-support option negotiation */
144 bool cas_legacy_guest_workaround;
145 sPAPROptionVector *ov5; /* QEMU-supported option vectors */
146 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
147 uint32_t max_compat_pvr;
149 /* Migration state */
151 bool htab_first_pass;
154 /* Pending DIMM unplug cache. It is populated when a LMB
155 * unplug starts. It can be regenerated if a migration
156 * occurs during the unplug process. */
157 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
161 MemoryHotplugState hotplug_memory;
163 const char *icp_type;
165 bool cmd_line_caps[SPAPR_CAP_NUM];
166 sPAPRCapabilities def, eff, mig;
170 #define H_BUSY 1 /* Hardware busy -- retry later */
171 #define H_CLOSED 2 /* Resource closed */
172 #define H_NOT_AVAILABLE 3
173 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
175 #define H_IN_PROGRESS 14 /* Kind of like busy */
176 #define H_PAGE_REGISTERED 15
177 #define H_PARTIAL_STORE 16
178 #define H_PENDING 17 /* returned from H_POLL_PENDING */
179 #define H_CONTINUE 18 /* Returned from H_Join on success */
180 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
181 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
182 is a good time to retry */
183 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
184 is a good time to retry */
185 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
186 is a good time to retry */
187 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
188 is a good time to retry */
189 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
190 is a good time to retry */
191 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
192 is a good time to retry */
193 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
194 #define H_HARDWARE -1 /* Hardware error */
195 #define H_FUNCTION -2 /* Function not supported */
196 #define H_PRIVILEGE -3 /* Caller not privileged */
197 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
198 #define H_BAD_MODE -5 /* Illegal msr value */
199 #define H_PTEG_FULL -6 /* PTEG is full */
200 #define H_NOT_FOUND -7 /* PTE was not found" */
201 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
203 #define H_AUTHORITY -10
204 #define H_PERMISSION -11
205 #define H_DROPPED -12
206 #define H_SOURCE_PARM -13
207 #define H_DEST_PARM -14
208 #define H_REMOTE_PARM -15
209 #define H_RESOURCE -16
210 #define H_ADAPTER_PARM -17
211 #define H_RH_PARM -18
212 #define H_RCQ_PARM -19
213 #define H_SCQ_PARM -20
214 #define H_EQ_PARM -21
215 #define H_RT_PARM -22
216 #define H_ST_PARM -23
217 #define H_SIGT_PARM -24
218 #define H_TOKEN_PARM -25
219 #define H_MLENGTH_PARM -27
220 #define H_MEM_PARM -28
221 #define H_MEM_ACCESS_PARM -29
222 #define H_ATTR_PARM -30
223 #define H_PORT_PARM -31
224 #define H_MCG_PARM -32
225 #define H_VL_PARM -33
226 #define H_TSIZE_PARM -34
227 #define H_TRACE_PARM -35
229 #define H_MASK_PARM -37
230 #define H_MCG_FULL -38
231 #define H_ALIAS_EXIST -39
232 #define H_P_COUNTER -40
233 #define H_TABLE_FULL -41
234 #define H_ALT_TABLE -42
235 #define H_MR_CONDITION -43
236 #define H_NOT_ENOUGH_RESOURCES -44
237 #define H_R_STATE -45
238 #define H_RESCINDEND -46
247 #define H_UNSUPPORTED_FLAG -256
248 #define H_MULTI_THREADS_ACTIVE -9005
251 /* Long Busy is a condition that can be returned by the firmware
252 * when a call cannot be completed now, but the identical call
253 * should be retried later. This prevents calls blocking in the
254 * firmware for long periods of time. Annoyingly the firmware can return
255 * a range of return codes, hinting at how long we should wait before
256 * retrying. If you don't care for the hint, the macro below is a good
257 * way to check for the long_busy return codes
259 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
260 && (x <= H_LONG_BUSY_END_RANGE))
263 #define H_LARGE_PAGE (1ULL<<(63-16))
264 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
265 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
266 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
267 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
268 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
269 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
270 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
271 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
272 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
273 #define H_ANDCOND (1ULL<<(63-33))
274 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
275 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
276 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
277 #define H_COPY_PAGE (1ULL<<(63-49))
278 #define H_N (1ULL<<(63-61))
279 #define H_PP1 (1ULL<<(63-62))
280 #define H_PP2 (1ULL<<(63-63))
282 /* Values for 2nd argument to H_SET_MODE */
283 #define H_SET_MODE_RESOURCE_SET_CIABR 1
284 #define H_SET_MODE_RESOURCE_SET_DAWR 2
285 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
286 #define H_SET_MODE_RESOURCE_LE 4
288 /* Flags for H_SET_MODE_RESOURCE_LE */
289 #define H_SET_MODE_ENDIAN_BIG 0
290 #define H_SET_MODE_ENDIAN_LITTLE 1
293 #define H_VASI_INVALID 0
294 #define H_VASI_ENABLED 1
295 #define H_VASI_ABORTED 2
296 #define H_VASI_SUSPENDING 3
297 #define H_VASI_SUSPENDED 4
298 #define H_VASI_RESUMED 5
299 #define H_VASI_COMPLETED 6
302 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
303 #define H_DABRX_KERNEL (1ULL<<(63-62))
304 #define H_DABRX_USER (1ULL<<(63-63))
306 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
307 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
308 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
309 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
310 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
311 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
312 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
313 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
314 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
315 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
316 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
318 /* Each control block has to be on a 4K boundary */
319 #define H_CB_ALIGNMENT 4096
321 /* pSeries hypervisor opcodes */
322 #define H_REMOVE 0x04
325 #define H_CLEAR_MOD 0x10
326 #define H_CLEAR_REF 0x14
327 #define H_PROTECT 0x18
328 #define H_GET_TCE 0x1c
329 #define H_PUT_TCE 0x20
330 #define H_SET_SPRG0 0x24
331 #define H_SET_DABR 0x28
332 #define H_PAGE_INIT 0x2c
333 #define H_SET_ASR 0x30
334 #define H_ASR_ON 0x34
335 #define H_ASR_OFF 0x38
336 #define H_LOGICAL_CI_LOAD 0x3c
337 #define H_LOGICAL_CI_STORE 0x40
338 #define H_LOGICAL_CACHE_LOAD 0x44
339 #define H_LOGICAL_CACHE_STORE 0x48
340 #define H_LOGICAL_ICBI 0x4c
341 #define H_LOGICAL_DCBF 0x50
342 #define H_GET_TERM_CHAR 0x54
343 #define H_PUT_TERM_CHAR 0x58
344 #define H_REAL_TO_LOGICAL 0x5c
345 #define H_HYPERVISOR_DATA 0x60
351 #define H_PERFMON 0x7c
352 #define H_MIGRATE_DMA 0x78
353 #define H_REGISTER_VPA 0xDC
355 #define H_CONFER 0xE4
357 #define H_GET_PPP 0xEC
358 #define H_SET_PPP 0xF0
361 #define H_REG_CRQ 0xFC
362 #define H_FREE_CRQ 0x100
363 #define H_VIO_SIGNAL 0x104
364 #define H_SEND_CRQ 0x108
365 #define H_COPY_RDMA 0x110
366 #define H_REGISTER_LOGICAL_LAN 0x114
367 #define H_FREE_LOGICAL_LAN 0x118
368 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
369 #define H_SEND_LOGICAL_LAN 0x120
370 #define H_BULK_REMOVE 0x124
371 #define H_MULTICAST_CTRL 0x130
372 #define H_SET_XDABR 0x134
373 #define H_STUFF_TCE 0x138
374 #define H_PUT_TCE_INDIRECT 0x13C
375 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
376 #define H_VTERM_PARTNER_INFO 0x150
377 #define H_REGISTER_VTERM 0x154
378 #define H_FREE_VTERM 0x158
379 #define H_RESET_EVENTS 0x15C
380 #define H_ALLOC_RESOURCE 0x160
381 #define H_FREE_RESOURCE 0x164
382 #define H_MODIFY_QP 0x168
383 #define H_QUERY_QP 0x16C
384 #define H_REREGISTER_PMR 0x170
385 #define H_REGISTER_SMR 0x174
386 #define H_QUERY_MR 0x178
387 #define H_QUERY_MW 0x17C
388 #define H_QUERY_HCA 0x180
389 #define H_QUERY_PORT 0x184
390 #define H_MODIFY_PORT 0x188
391 #define H_DEFINE_AQP1 0x18C
392 #define H_GET_TRACE_BUFFER 0x190
393 #define H_DEFINE_AQP0 0x194
394 #define H_RESIZE_MR 0x198
395 #define H_ATTACH_MCQP 0x19C
396 #define H_DETACH_MCQP 0x1A0
397 #define H_CREATE_RPT 0x1A4
398 #define H_REMOVE_RPT 0x1A8
399 #define H_REGISTER_RPAGES 0x1AC
400 #define H_DISABLE_AND_GETC 0x1B0
401 #define H_ERROR_DATA 0x1B4
402 #define H_GET_HCA_INFO 0x1B8
403 #define H_GET_PERF_COUNT 0x1BC
404 #define H_MANAGE_TRACE 0x1C0
405 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
406 #define H_QUERY_INT_STATE 0x1E4
407 #define H_POLL_PENDING 0x1D8
408 #define H_ILLAN_ATTRIBUTES 0x244
409 #define H_MODIFY_HEA_QP 0x250
410 #define H_QUERY_HEA_QP 0x254
411 #define H_QUERY_HEA 0x258
412 #define H_QUERY_HEA_PORT 0x25C
413 #define H_MODIFY_HEA_PORT 0x260
414 #define H_REG_BCMC 0x264
415 #define H_DEREG_BCMC 0x268
416 #define H_REGISTER_HEA_RPAGES 0x26C
417 #define H_DISABLE_AND_GET_HEA 0x270
418 #define H_GET_HEA_INFO 0x274
419 #define H_ALLOC_HEA_RESOURCE 0x278
420 #define H_ADD_CONN 0x284
421 #define H_DEL_CONN 0x288
423 #define H_VASI_STATE 0x2A4
424 #define H_ENABLE_CRQ 0x2B0
425 #define H_GET_EM_PARMS 0x2B8
426 #define H_SET_MPP 0x2D0
427 #define H_GET_MPP 0x2D4
428 #define H_XIRR_X 0x2FC
429 #define H_RANDOM 0x300
430 #define H_SET_MODE 0x31C
431 #define H_RESIZE_HPT_PREPARE 0x36C
432 #define H_RESIZE_HPT_COMMIT 0x370
433 #define H_CLEAN_SLB 0x374
434 #define H_INVALIDATE_PID 0x378
435 #define H_REGISTER_PROC_TBL 0x37C
436 #define H_SIGNAL_SYS_RESET 0x380
437 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
439 /* The hcalls above are standardized in PAPR and implemented by pHyp
442 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
443 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
444 * for "platform-specific" hcalls.
446 #define KVMPPC_HCALL_BASE 0xf000
447 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
448 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
449 /* Client Architecture support */
450 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
451 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS
453 typedef struct sPAPRDeviceTreeUpdateHeader {
455 } sPAPRDeviceTreeUpdateHeader;
457 #define hcall_dprintf(fmt, ...) \
459 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
462 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
466 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
467 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
470 /* ibm,set-eeh-option */
471 #define RTAS_EEH_DISABLE 0
472 #define RTAS_EEH_ENABLE 1
473 #define RTAS_EEH_THAW_IO 2
474 #define RTAS_EEH_THAW_DMA 3
476 /* ibm,get-config-addr-info2 */
477 #define RTAS_GET_PE_ADDR 0
478 #define RTAS_GET_PE_MODE 1
479 #define RTAS_PE_MODE_NONE 0
480 #define RTAS_PE_MODE_NOT_SHARED 1
481 #define RTAS_PE_MODE_SHARED 2
483 /* ibm,read-slot-reset-state2 */
484 #define RTAS_EEH_PE_STATE_NORMAL 0
485 #define RTAS_EEH_PE_STATE_RESET 1
486 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
487 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
488 #define RTAS_EEH_PE_STATE_UNAVAIL 5
489 #define RTAS_EEH_NOT_SUPPORT 0
490 #define RTAS_EEH_SUPPORT 1
491 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
492 #define RTAS_EEH_PE_RECOVER_INFO 0
494 /* ibm,set-slot-reset */
495 #define RTAS_SLOT_RESET_DEACTIVATE 0
496 #define RTAS_SLOT_RESET_HOT 1
497 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
499 /* ibm,slot-error-detail */
500 #define RTAS_SLOT_TEMP_ERR_LOG 1
501 #define RTAS_SLOT_PERM_ERR_LOG 2
503 /* RTAS return codes */
504 #define RTAS_OUT_SUCCESS 0
505 #define RTAS_OUT_NO_ERRORS_FOUND 1
506 #define RTAS_OUT_HW_ERROR -1
507 #define RTAS_OUT_BUSY -2
508 #define RTAS_OUT_PARAM_ERROR -3
509 #define RTAS_OUT_NOT_SUPPORTED -3
510 #define RTAS_OUT_NO_SUCH_INDICATOR -3
511 #define RTAS_OUT_NOT_AUTHORIZED -9002
512 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
514 /* DDW pagesize mask values from ibm,query-pe-dma-window */
515 #define RTAS_DDW_PGSIZE_4K 0x01
516 #define RTAS_DDW_PGSIZE_64K 0x02
517 #define RTAS_DDW_PGSIZE_16M 0x04
518 #define RTAS_DDW_PGSIZE_32M 0x08
519 #define RTAS_DDW_PGSIZE_64M 0x10
520 #define RTAS_DDW_PGSIZE_128M 0x20
521 #define RTAS_DDW_PGSIZE_256M 0x40
522 #define RTAS_DDW_PGSIZE_16G 0x80
525 #define RTAS_TOKEN_BASE 0x2000
527 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
528 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
529 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
530 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
531 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
532 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
533 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
534 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
535 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
536 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
537 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
538 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
539 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
540 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
541 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
542 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
543 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
544 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
545 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
546 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
547 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
548 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
549 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
550 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
551 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
552 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
553 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
554 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
555 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
556 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
557 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
558 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
559 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
560 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
561 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
562 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
563 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
564 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
565 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
566 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
567 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
568 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
570 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
572 /* RTAS ibm,get-system-parameter token values */
573 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
574 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
575 #define RTAS_SYSPARM_UUID 48
577 /* RTAS indicator/sensor types
579 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
581 * NOTE: currently only DR-related sensors are implemented here
583 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
584 #define RTAS_SENSOR_TYPE_DR 9002
585 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
586 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
588 /* Possible values for the platform-processor-diagnostics-run-mode parameter
589 * of the RTAS ibm,get-system-parameter call.
591 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
592 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
593 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
594 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
596 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
598 return addr & ~0xF000000000000000ULL;
601 static inline uint32_t rtas_ld(target_ulong phys, int n)
603 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
606 static inline uint64_t rtas_ldq(target_ulong phys, int n)
608 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
611 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
613 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
616 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
618 uint32_t nargs, target_ulong args,
619 uint32_t nret, target_ulong rets);
620 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
621 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
622 uint32_t token, uint32_t nargs, target_ulong args,
623 uint32_t nret, target_ulong rets);
624 void spapr_dt_rtas_tokens(void *fdt, int rtas);
625 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
627 #define SPAPR_TCE_PAGE_SHIFT 12
628 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
629 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
631 #define SPAPR_VIO_BASE_LIOBN 0x00000000
632 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
633 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
634 (0x80000000 | ((phb_index) << 8) | (window_num))
635 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
636 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
638 #define RTAS_ERROR_LOG_MAX 2048
640 #define RTAS_EVENT_SCAN_RATE 1
642 /* This helper should be used to encode interrupt specifiers when the related
643 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
644 * VIO devices, RTAS event sources and PHBs).
646 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
648 intspec[0] = cpu_to_be32(irq);
649 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
652 typedef struct sPAPRTCETable sPAPRTCETable;
654 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
655 #define SPAPR_TCE_TABLE(obj) \
656 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
658 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
659 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
660 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
662 struct sPAPRTCETable {
669 uint32_t mig_nb_table;
675 IOMMUMemoryRegion iommu;
676 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
677 QLIST_ENTRY(sPAPRTCETable) list;
680 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
682 struct sPAPREventLogEntry {
684 uint32_t extended_length;
686 QTAILQ_ENTRY(sPAPREventLogEntry) next;
689 void spapr_events_init(sPAPRMachineState *sm);
690 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
691 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
692 target_ulong addr, target_ulong size,
693 sPAPROptionVector *ov5_updates);
694 void close_htab_fd(sPAPRMachineState *spapr);
695 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
696 void spapr_free_hpt(sPAPRMachineState *spapr);
697 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
698 void spapr_tce_table_enable(sPAPRTCETable *tcet,
699 uint32_t page_shift, uint64_t bus_offset,
701 void spapr_tce_table_disable(sPAPRTCETable *tcet);
702 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
704 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
705 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
706 uint32_t liobn, uint64_t window, uint32_t size);
707 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
708 sPAPRTCETable *tcet);
709 void spapr_pci_switch_vga(bool big_endian);
710 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
711 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
712 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
714 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
716 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
717 uint32_t count, uint32_t index);
718 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
719 uint32_t count, uint32_t index);
720 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
721 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
723 void spapr_clear_pending_events(sPAPRMachineState *spapr);
725 /* CPU and LMB DRC release callbacks. */
726 void spapr_core_release(DeviceState *dev);
727 void spapr_lmb_release(DeviceState *dev);
729 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
730 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
732 #define TYPE_SPAPR_RNG "spapr-rng"
734 int spapr_rng_populate_dt(void *fdt);
736 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
739 * This defines the maximum number of DIMM slots we can have for sPAPR
740 * guest. This is not defined by sPAPR but we are defining it to 32 slots
741 * based on default number of slots provided by PowerPC kernel.
743 #define SPAPR_MAX_RAM_SLOTS 32
745 /* 1GB alignment for hotplug memory region */
746 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
749 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
750 * property under ibm,dynamic-reconfiguration-memory node.
752 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
755 * Defines for flag value in ibm,dynamic-memory property under
756 * ibm,dynamic-reconfiguration-memory node.
758 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
759 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
760 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
762 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
764 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
766 int spapr_vcpu_id(PowerPCCPU *cpu);
767 PowerPCCPU *spapr_find_cpu(int vcpu_id);
769 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
771 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
772 bool align, Error **errp);
773 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
774 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
777 int spapr_caps_pre_load(void *opaque);
778 int spapr_caps_pre_save(void *opaque);
781 * Handling of optional capabilities
783 extern const VMStateDescription vmstate_spapr_cap_htm;
784 extern const VMStateDescription vmstate_spapr_cap_vsx;
785 extern const VMStateDescription vmstate_spapr_cap_dfp;
786 extern const VMStateDescription vmstate_spapr_cap_cfpc;
787 extern const VMStateDescription vmstate_spapr_cap_sbbc;
789 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
791 return spapr->eff.caps[cap];
794 void spapr_caps_reset(sPAPRMachineState *spapr);
795 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
796 int spapr_caps_post_migration(sPAPRMachineState *spapr);
798 #endif /* HW_SPAPR_H */