target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #if !defined(CONFIG_USER_ONLY)
  25 #include "hw/loader.h"
  26 #endif
  27 #include "hw/arm/arm.h"
  28 #include "sysemu/sysemu.h"
  29 #include "sysemu/kvm.h"
  30
  31 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     ARMCPU *cpu = ARM_CPU(cs);
  34
  35     cpu->env.regs[15] = value;
  36 }
  37
  38 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  39 {
  40     /* Reset a single ARMCPRegInfo register */
  41     ARMCPRegInfo *ri = value;
  42     ARMCPU *cpu = opaque;
  43
  44     if (ri->type & ARM_CP_SPECIAL) {
  45         return;
  46     }
  47
  48     if (ri->resetfn) {
  49         ri->resetfn(&cpu->env, ri);
  50         return;
  51     }
  52
  53     /* A zero offset is never possible as it would be regs[0]
  54      * so we use it to indicate that reset is being handled elsewhere.
  55      * This is basically only used for fields in non-core coprocessors
  56      * (like the pxa2xx ones).
  57      */
  58     if (!ri->fieldoffset) {
  59         return;
  60     }
  61
  62     if (ri->type & ARM_CP_64BIT) {
  63         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  64     } else {
  65         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  66     }
  67 }
  68
  69 /* CPUClass::reset() */
  70 static void arm_cpu_reset(CPUState *s)
  71 {
  72     ARMCPU *cpu = ARM_CPU(s);
  73     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  74     CPUARMState *env = &cpu->env;
  75
  76     acc->parent_reset(s);
  77
  78     memset(env, 0, offsetof(CPUARMState, breakpoints));
  79     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  80     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  81     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  82     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  83
  84     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  85         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  86     }
  87
  88     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  89         /* 64 bit CPUs always start in 64 bit mode */
  90         env->aarch64 = 1;
  91     }
  92
  93 #if defined(CONFIG_USER_ONLY)
  94     env->uncached_cpsr = ARM_CPU_MODE_USR;
  95     /* For user mode we must enable access to coprocessors */
  96     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  97     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  98         env->cp15.c15_cpar = 3;
  99     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 100         env->cp15.c15_cpar = 1;
 101     }
 102 #else
 103     /* SVC mode with interrupts disabled.  */
 104     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 105     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 106        clear at reset.  Initial SP and PC are loaded from ROM.  */
 107     if (IS_M(env)) {
 108         uint32_t pc;
 109         uint8_t *rom;
 110         env->uncached_cpsr &= ~CPSR_I;
 111         rom = rom_ptr(0);
 112         if (rom) {
 113             /* We should really use ldl_phys here, in case the guest
 114                modified flash and reset itself.  However images
 115                loaded via -kernel have not been copied yet, so load the
 116                values directly from there.  */
 117             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 118             pc = ldl_p(rom + 4);
 119             env->thumb = pc & 1;
 120             env->regs[15] = pc & ~1;
 121         }
 122     }
 123     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 124 #endif
 125     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 126     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 127     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 128     set_float_detect_tininess(float_tininess_before_rounding,
 129                               &env->vfp.fp_status);
 130     set_float_detect_tininess(float_tininess_before_rounding,
 131                               &env->vfp.standard_fp_status);
 132     tlb_flush(env, 1);
 133     /* Reset is a state change for some CPUARMState fields which we
 134      * bake assumptions about into translated code, so we need to
 135      * tb_flush().
 136      */
 137     tb_flush(env);
 138 }
 139
 140 #ifndef CONFIG_USER_ONLY
 141 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 142 {
 143     ARMCPU *cpu = opaque;
 144     CPUState *cs = CPU(cpu);
 145
 146     switch (irq) {
 147     case ARM_CPU_IRQ:
 148         if (level) {
 149             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 150         } else {
 151             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 152         }
 153         break;
 154     case ARM_CPU_FIQ:
 155         if (level) {
 156             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 157         } else {
 158             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 159         }
 160         break;
 161     default:
 162         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 163     }
 164 }
 165
 166 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 167 {
 168 #ifdef CONFIG_KVM
 169     ARMCPU *cpu = opaque;
 170     CPUState *cs = CPU(cpu);
 171     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 172
 173     switch (irq) {
 174     case ARM_CPU_IRQ:
 175         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 176         break;
 177     case ARM_CPU_FIQ:
 178         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 179         break;
 180     default:
 181         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 182     }
 183     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 184     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 185 #endif
 186 }
 187 #endif
 188
 189 static inline void set_feature(CPUARMState *env, int feature)
 190 {
 191     env->features |= 1ULL << feature;
 192 }
 193
 194 static void arm_cpu_initfn(Object *obj)
 195 {
 196     CPUState *cs = CPU(obj);
 197     ARMCPU *cpu = ARM_CPU(obj);
 198     static bool inited;
 199
 200     cs->env_ptr = &cpu->env;
 201     cpu_exec_init(&cpu->env);
 202     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 203                                          g_free, g_free);
 204
 205 #ifndef CONFIG_USER_ONLY
 206     /* Our inbound IRQ and FIQ lines */
 207     if (kvm_enabled()) {
 208         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 209     } else {
 210         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 211     }
 212
 213     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 214                                                 arm_gt_ptimer_cb, cpu);
 215     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 216                                                 arm_gt_vtimer_cb, cpu);
 217     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 218                        ARRAY_SIZE(cpu->gt_timer_outputs));
 219 #endif
 220
 221     /* DTB consumers generally don't in fact care what the 'compatible'
 222      * string is, so always provide some string and trust that a hypothetical
 223      * picky DTB consumer will also provide a helpful error message.
 224      */
 225     cpu->dtb_compatible = "qemu,unknown";
 226     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 227
 228     if (tcg_enabled() && !inited) {
 229         inited = true;
 230         arm_translate_init();
 231     }
 232 }
 233
 234 static void arm_cpu_finalizefn(Object *obj)
 235 {
 236     ARMCPU *cpu = ARM_CPU(obj);
 237     g_hash_table_destroy(cpu->cp_regs);
 238 }
 239
 240 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 241 {
 242     CPUState *cs = CPU(dev);
 243     ARMCPU *cpu = ARM_CPU(dev);
 244     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 245     CPUARMState *env = &cpu->env;
 246
 247     /* Some features automatically imply others: */
 248     if (arm_feature(env, ARM_FEATURE_V8)) {
 249         set_feature(env, ARM_FEATURE_V7);
 250         set_feature(env, ARM_FEATURE_ARM_DIV);
 251         set_feature(env, ARM_FEATURE_LPAE);
 252     }
 253     if (arm_feature(env, ARM_FEATURE_V7)) {
 254         set_feature(env, ARM_FEATURE_VAPA);
 255         set_feature(env, ARM_FEATURE_THUMB2);
 256         set_feature(env, ARM_FEATURE_MPIDR);
 257         if (!arm_feature(env, ARM_FEATURE_M)) {
 258             set_feature(env, ARM_FEATURE_V6K);
 259         } else {
 260             set_feature(env, ARM_FEATURE_V6);
 261         }
 262     }
 263     if (arm_feature(env, ARM_FEATURE_V6K)) {
 264         set_feature(env, ARM_FEATURE_V6);
 265         set_feature(env, ARM_FEATURE_MVFR);
 266     }
 267     if (arm_feature(env, ARM_FEATURE_V6)) {
 268         set_feature(env, ARM_FEATURE_V5);
 269         if (!arm_feature(env, ARM_FEATURE_M)) {
 270             set_feature(env, ARM_FEATURE_AUXCR);
 271         }
 272     }
 273     if (arm_feature(env, ARM_FEATURE_V5)) {
 274         set_feature(env, ARM_FEATURE_V4T);
 275     }
 276     if (arm_feature(env, ARM_FEATURE_M)) {
 277         set_feature(env, ARM_FEATURE_THUMB_DIV);
 278     }
 279     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 280         set_feature(env, ARM_FEATURE_THUMB_DIV);
 281     }
 282     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 283         set_feature(env, ARM_FEATURE_VFP3);
 284     }
 285     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 286         set_feature(env, ARM_FEATURE_VFP);
 287     }
 288     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 289         set_feature(env, ARM_FEATURE_V7MP);
 290         set_feature(env, ARM_FEATURE_PXN);
 291     }
 292
 293     register_cp_regs_for_features(cpu);
 294     arm_cpu_register_gdb_regs_for_features(cpu);
 295
 296     init_cpreg_list(cpu);
 297
 298     cpu_reset(cs);
 299     qemu_init_vcpu(cs);
 300
 301     acc->parent_realize(dev, errp);
 302 }
 303
 304 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 305 {
 306     ObjectClass *oc;
 307     char *typename;
 308
 309     if (!cpu_model) {
 310         return NULL;
 311     }
 312
 313     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 314     oc = object_class_by_name(typename);
 315     g_free(typename);
 316     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 317         object_class_is_abstract(oc)) {
 318         return NULL;
 319     }
 320     return oc;
 321 }
 322
 323 /* CPU models. These are not needed for the AArch64 linux-user build. */
 324 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 325
 326 static void arm926_initfn(Object *obj)
 327 {
 328     ARMCPU *cpu = ARM_CPU(obj);
 329
 330     cpu->dtb_compatible = "arm,arm926";
 331     set_feature(&cpu->env, ARM_FEATURE_V5);
 332     set_feature(&cpu->env, ARM_FEATURE_VFP);
 333     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 334     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 335     cpu->midr = 0x41069265;
 336     cpu->reset_fpsid = 0x41011090;
 337     cpu->ctr = 0x1dd20d2;
 338     cpu->reset_sctlr = 0x00090078;
 339 }
 340
 341 static void arm946_initfn(Object *obj)
 342 {
 343     ARMCPU *cpu = ARM_CPU(obj);
 344
 345     cpu->dtb_compatible = "arm,arm946";
 346     set_feature(&cpu->env, ARM_FEATURE_V5);
 347     set_feature(&cpu->env, ARM_FEATURE_MPU);
 348     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 349     cpu->midr = 0x41059461;
 350     cpu->ctr = 0x0f004006;
 351     cpu->reset_sctlr = 0x00000078;
 352 }
 353
 354 static void arm1026_initfn(Object *obj)
 355 {
 356     ARMCPU *cpu = ARM_CPU(obj);
 357
 358     cpu->dtb_compatible = "arm,arm1026";
 359     set_feature(&cpu->env, ARM_FEATURE_V5);
 360     set_feature(&cpu->env, ARM_FEATURE_VFP);
 361     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 362     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 363     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 364     cpu->midr = 0x4106a262;
 365     cpu->reset_fpsid = 0x410110a0;
 366     cpu->ctr = 0x1dd20d2;
 367     cpu->reset_sctlr = 0x00090078;
 368     cpu->reset_auxcr = 1;
 369     {
 370         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 371         ARMCPRegInfo ifar = {
 372             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 373             .access = PL1_RW,
 374             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 375             .resetvalue = 0
 376         };
 377         define_one_arm_cp_reg(cpu, &ifar);
 378     }
 379 }
 380
 381 static void arm1136_r2_initfn(Object *obj)
 382 {
 383     ARMCPU *cpu = ARM_CPU(obj);
 384     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 385      * older core than plain "arm1136". In particular this does not
 386      * have the v6K features.
 387      * These ID register values are correct for 1136 but may be wrong
 388      * for 1136_r2 (in particular r0p2 does not actually implement most
 389      * of the ID registers).
 390      */
 391
 392     cpu->dtb_compatible = "arm,arm1136";
 393     set_feature(&cpu->env, ARM_FEATURE_V6);
 394     set_feature(&cpu->env, ARM_FEATURE_VFP);
 395     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 396     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 397     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 398     cpu->midr = 0x4107b362;
 399     cpu->reset_fpsid = 0x410120b4;
 400     cpu->mvfr0 = 0x11111111;
 401     cpu->mvfr1 = 0x00000000;
 402     cpu->ctr = 0x1dd20d2;
 403     cpu->reset_sctlr = 0x00050078;
 404     cpu->id_pfr0 = 0x111;
 405     cpu->id_pfr1 = 0x1;
 406     cpu->id_dfr0 = 0x2;
 407     cpu->id_afr0 = 0x3;
 408     cpu->id_mmfr0 = 0x01130003;
 409     cpu->id_mmfr1 = 0x10030302;
 410     cpu->id_mmfr2 = 0x01222110;
 411     cpu->id_isar0 = 0x00140011;
 412     cpu->id_isar1 = 0x12002111;
 413     cpu->id_isar2 = 0x11231111;
 414     cpu->id_isar3 = 0x01102131;
 415     cpu->id_isar4 = 0x141;
 416     cpu->reset_auxcr = 7;
 417 }
 418
 419 static void arm1136_initfn(Object *obj)
 420 {
 421     ARMCPU *cpu = ARM_CPU(obj);
 422
 423     cpu->dtb_compatible = "arm,arm1136";
 424     set_feature(&cpu->env, ARM_FEATURE_V6K);
 425     set_feature(&cpu->env, ARM_FEATURE_V6);
 426     set_feature(&cpu->env, ARM_FEATURE_VFP);
 427     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 428     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 429     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 430     cpu->midr = 0x4117b363;
 431     cpu->reset_fpsid = 0x410120b4;
 432     cpu->mvfr0 = 0x11111111;
 433     cpu->mvfr1 = 0x00000000;
 434     cpu->ctr = 0x1dd20d2;
 435     cpu->reset_sctlr = 0x00050078;
 436     cpu->id_pfr0 = 0x111;
 437     cpu->id_pfr1 = 0x1;
 438     cpu->id_dfr0 = 0x2;
 439     cpu->id_afr0 = 0x3;
 440     cpu->id_mmfr0 = 0x01130003;
 441     cpu->id_mmfr1 = 0x10030302;
 442     cpu->id_mmfr2 = 0x01222110;
 443     cpu->id_isar0 = 0x00140011;
 444     cpu->id_isar1 = 0x12002111;
 445     cpu->id_isar2 = 0x11231111;
 446     cpu->id_isar3 = 0x01102131;
 447     cpu->id_isar4 = 0x141;
 448     cpu->reset_auxcr = 7;
 449 }
 450
 451 static void arm1176_initfn(Object *obj)
 452 {
 453     ARMCPU *cpu = ARM_CPU(obj);
 454
 455     cpu->dtb_compatible = "arm,arm1176";
 456     set_feature(&cpu->env, ARM_FEATURE_V6K);
 457     set_feature(&cpu->env, ARM_FEATURE_VFP);
 458     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 459     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 460     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 461     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 462     cpu->midr = 0x410fb767;
 463     cpu->reset_fpsid = 0x410120b5;
 464     cpu->mvfr0 = 0x11111111;
 465     cpu->mvfr1 = 0x00000000;
 466     cpu->ctr = 0x1dd20d2;
 467     cpu->reset_sctlr = 0x00050078;
 468     cpu->id_pfr0 = 0x111;
 469     cpu->id_pfr1 = 0x11;
 470     cpu->id_dfr0 = 0x33;
 471     cpu->id_afr0 = 0;
 472     cpu->id_mmfr0 = 0x01130003;
 473     cpu->id_mmfr1 = 0x10030302;
 474     cpu->id_mmfr2 = 0x01222100;
 475     cpu->id_isar0 = 0x0140011;
 476     cpu->id_isar1 = 0x12002111;
 477     cpu->id_isar2 = 0x11231121;
 478     cpu->id_isar3 = 0x01102131;
 479     cpu->id_isar4 = 0x01141;
 480     cpu->reset_auxcr = 7;
 481 }
 482
 483 static void arm11mpcore_initfn(Object *obj)
 484 {
 485     ARMCPU *cpu = ARM_CPU(obj);
 486
 487     cpu->dtb_compatible = "arm,arm11mpcore";
 488     set_feature(&cpu->env, ARM_FEATURE_V6K);
 489     set_feature(&cpu->env, ARM_FEATURE_VFP);
 490     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 491     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 492     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 493     cpu->midr = 0x410fb022;
 494     cpu->reset_fpsid = 0x410120b4;
 495     cpu->mvfr0 = 0x11111111;
 496     cpu->mvfr1 = 0x00000000;
 497     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 498     cpu->id_pfr0 = 0x111;
 499     cpu->id_pfr1 = 0x1;
 500     cpu->id_dfr0 = 0;
 501     cpu->id_afr0 = 0x2;
 502     cpu->id_mmfr0 = 0x01100103;
 503     cpu->id_mmfr1 = 0x10020302;
 504     cpu->id_mmfr2 = 0x01222000;
 505     cpu->id_isar0 = 0x00100011;
 506     cpu->id_isar1 = 0x12002111;
 507     cpu->id_isar2 = 0x11221011;
 508     cpu->id_isar3 = 0x01102131;
 509     cpu->id_isar4 = 0x141;
 510     cpu->reset_auxcr = 1;
 511 }
 512
 513 static void cortex_m3_initfn(Object *obj)
 514 {
 515     ARMCPU *cpu = ARM_CPU(obj);
 516     set_feature(&cpu->env, ARM_FEATURE_V7);
 517     set_feature(&cpu->env, ARM_FEATURE_M);
 518     cpu->midr = 0x410fc231;
 519 }
 520
 521 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 522 {
 523 #ifndef CONFIG_USER_ONLY
 524     CPUClass *cc = CPU_CLASS(oc);
 525
 526     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 527 #endif
 528 }
 529
 530 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 531     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 532       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 533     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 534       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 535     REGINFO_SENTINEL
 536 };
 537
 538 static void cortex_a8_initfn(Object *obj)
 539 {
 540     ARMCPU *cpu = ARM_CPU(obj);
 541
 542     cpu->dtb_compatible = "arm,cortex-a8";
 543     set_feature(&cpu->env, ARM_FEATURE_V7);
 544     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 545     set_feature(&cpu->env, ARM_FEATURE_NEON);
 546     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 547     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 548     cpu->midr = 0x410fc080;
 549     cpu->reset_fpsid = 0x410330c0;
 550     cpu->mvfr0 = 0x11110222;
 551     cpu->mvfr1 = 0x00011100;
 552     cpu->ctr = 0x82048004;
 553     cpu->reset_sctlr = 0x00c50078;
 554     cpu->id_pfr0 = 0x1031;
 555     cpu->id_pfr1 = 0x11;
 556     cpu->id_dfr0 = 0x400;
 557     cpu->id_afr0 = 0;
 558     cpu->id_mmfr0 = 0x31100003;
 559     cpu->id_mmfr1 = 0x20000000;
 560     cpu->id_mmfr2 = 0x01202000;
 561     cpu->id_mmfr3 = 0x11;
 562     cpu->id_isar0 = 0x00101111;
 563     cpu->id_isar1 = 0x12112111;
 564     cpu->id_isar2 = 0x21232031;
 565     cpu->id_isar3 = 0x11112131;
 566     cpu->id_isar4 = 0x00111142;
 567     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 568     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 569     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 570     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 571     cpu->reset_auxcr = 2;
 572     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 573 }
 574
 575 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 576     /* power_control should be set to maximum latency. Again,
 577      * default to 0 and set by private hook
 578      */
 579     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 580       .access = PL1_RW, .resetvalue = 0,
 581       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 582     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 583       .access = PL1_RW, .resetvalue = 0,
 584       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 585     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 586       .access = PL1_RW, .resetvalue = 0,
 587       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 588     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 589       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 590     /* TLB lockdown control */
 591     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 592       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 593     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 594       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 595     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 596       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 597     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 598       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 599     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 600       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 601     REGINFO_SENTINEL
 602 };
 603
 604 static void cortex_a9_initfn(Object *obj)
 605 {
 606     ARMCPU *cpu = ARM_CPU(obj);
 607
 608     cpu->dtb_compatible = "arm,cortex-a9";
 609     set_feature(&cpu->env, ARM_FEATURE_V7);
 610     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 611     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 612     set_feature(&cpu->env, ARM_FEATURE_NEON);
 613     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 614     /* Note that A9 supports the MP extensions even for
 615      * A9UP and single-core A9MP (which are both different
 616      * and valid configurations; we don't model A9UP).
 617      */
 618     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 619     cpu->midr = 0x410fc090;
 620     cpu->reset_fpsid = 0x41033090;
 621     cpu->mvfr0 = 0x11110222;
 622     cpu->mvfr1 = 0x01111111;
 623     cpu->ctr = 0x80038003;
 624     cpu->reset_sctlr = 0x00c50078;
 625     cpu->id_pfr0 = 0x1031;
 626     cpu->id_pfr1 = 0x11;
 627     cpu->id_dfr0 = 0x000;
 628     cpu->id_afr0 = 0;
 629     cpu->id_mmfr0 = 0x00100103;
 630     cpu->id_mmfr1 = 0x20000000;
 631     cpu->id_mmfr2 = 0x01230000;
 632     cpu->id_mmfr3 = 0x00002111;
 633     cpu->id_isar0 = 0x00101111;
 634     cpu->id_isar1 = 0x13112111;
 635     cpu->id_isar2 = 0x21232041;
 636     cpu->id_isar3 = 0x11112131;
 637     cpu->id_isar4 = 0x00111142;
 638     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 639     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 640     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 641     {
 642         ARMCPRegInfo cbar = {
 643             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 644             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 645             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 646         };
 647         define_one_arm_cp_reg(cpu, &cbar);
 648         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 649     }
 650 }
 651
 652 #ifndef CONFIG_USER_ONLY
 653 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 654                            uint64_t *value)
 655 {
 656     /* Linux wants the number of processors from here.
 657      * Might as well set the interrupt-controller bit too.
 658      */
 659     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 660     return 0;
 661 }
 662 #endif
 663
 664 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 665 #ifndef CONFIG_USER_ONLY
 666     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 667       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 668       .writefn = arm_cp_write_ignore, },
 669 #endif
 670     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 671       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 672     REGINFO_SENTINEL
 673 };
 674
 675 static void cortex_a15_initfn(Object *obj)
 676 {
 677     ARMCPU *cpu = ARM_CPU(obj);
 678
 679     cpu->dtb_compatible = "arm,cortex-a15";
 680     set_feature(&cpu->env, ARM_FEATURE_V7);
 681     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 682     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 683     set_feature(&cpu->env, ARM_FEATURE_NEON);
 684     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 685     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 686     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 687     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 688     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 689     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 690     cpu->midr = 0x412fc0f1;
 691     cpu->reset_fpsid = 0x410430f0;
 692     cpu->mvfr0 = 0x10110222;
 693     cpu->mvfr1 = 0x11111111;
 694     cpu->ctr = 0x8444c004;
 695     cpu->reset_sctlr = 0x00c50078;
 696     cpu->id_pfr0 = 0x00001131;
 697     cpu->id_pfr1 = 0x00011011;
 698     cpu->id_dfr0 = 0x02010555;
 699     cpu->id_afr0 = 0x00000000;
 700     cpu->id_mmfr0 = 0x10201105;
 701     cpu->id_mmfr1 = 0x20000000;
 702     cpu->id_mmfr2 = 0x01240000;
 703     cpu->id_mmfr3 = 0x02102211;
 704     cpu->id_isar0 = 0x02101110;
 705     cpu->id_isar1 = 0x13112111;
 706     cpu->id_isar2 = 0x21232041;
 707     cpu->id_isar3 = 0x11112131;
 708     cpu->id_isar4 = 0x10011142;
 709     cpu->clidr = 0x0a200023;
 710     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 711     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 712     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 713     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 714 }
 715
 716 static void ti925t_initfn(Object *obj)
 717 {
 718     ARMCPU *cpu = ARM_CPU(obj);
 719     set_feature(&cpu->env, ARM_FEATURE_V4T);
 720     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 721     cpu->midr = ARM_CPUID_TI925T;
 722     cpu->ctr = 0x5109149;
 723     cpu->reset_sctlr = 0x00000070;
 724 }
 725
 726 static void sa1100_initfn(Object *obj)
 727 {
 728     ARMCPU *cpu = ARM_CPU(obj);
 729
 730     cpu->dtb_compatible = "intel,sa1100";
 731     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 732     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 733     cpu->midr = 0x4401A11B;
 734     cpu->reset_sctlr = 0x00000070;
 735 }
 736
 737 static void sa1110_initfn(Object *obj)
 738 {
 739     ARMCPU *cpu = ARM_CPU(obj);
 740     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 741     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 742     cpu->midr = 0x6901B119;
 743     cpu->reset_sctlr = 0x00000070;
 744 }
 745
 746 static void pxa250_initfn(Object *obj)
 747 {
 748     ARMCPU *cpu = ARM_CPU(obj);
 749
 750     cpu->dtb_compatible = "marvell,xscale";
 751     set_feature(&cpu->env, ARM_FEATURE_V5);
 752     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 753     cpu->midr = 0x69052100;
 754     cpu->ctr = 0xd172172;
 755     cpu->reset_sctlr = 0x00000078;
 756 }
 757
 758 static void pxa255_initfn(Object *obj)
 759 {
 760     ARMCPU *cpu = ARM_CPU(obj);
 761
 762     cpu->dtb_compatible = "marvell,xscale";
 763     set_feature(&cpu->env, ARM_FEATURE_V5);
 764     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 765     cpu->midr = 0x69052d00;
 766     cpu->ctr = 0xd172172;
 767     cpu->reset_sctlr = 0x00000078;
 768 }
 769
 770 static void pxa260_initfn(Object *obj)
 771 {
 772     ARMCPU *cpu = ARM_CPU(obj);
 773
 774     cpu->dtb_compatible = "marvell,xscale";
 775     set_feature(&cpu->env, ARM_FEATURE_V5);
 776     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 777     cpu->midr = 0x69052903;
 778     cpu->ctr = 0xd172172;
 779     cpu->reset_sctlr = 0x00000078;
 780 }
 781
 782 static void pxa261_initfn(Object *obj)
 783 {
 784     ARMCPU *cpu = ARM_CPU(obj);
 785
 786     cpu->dtb_compatible = "marvell,xscale";
 787     set_feature(&cpu->env, ARM_FEATURE_V5);
 788     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 789     cpu->midr = 0x69052d05;
 790     cpu->ctr = 0xd172172;
 791     cpu->reset_sctlr = 0x00000078;
 792 }
 793
 794 static void pxa262_initfn(Object *obj)
 795 {
 796     ARMCPU *cpu = ARM_CPU(obj);
 797
 798     cpu->dtb_compatible = "marvell,xscale";
 799     set_feature(&cpu->env, ARM_FEATURE_V5);
 800     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 801     cpu->midr = 0x69052d06;
 802     cpu->ctr = 0xd172172;
 803     cpu->reset_sctlr = 0x00000078;
 804 }
 805
 806 static void pxa270a0_initfn(Object *obj)
 807 {
 808     ARMCPU *cpu = ARM_CPU(obj);
 809
 810     cpu->dtb_compatible = "marvell,xscale";
 811     set_feature(&cpu->env, ARM_FEATURE_V5);
 812     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 813     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 814     cpu->midr = 0x69054110;
 815     cpu->ctr = 0xd172172;
 816     cpu->reset_sctlr = 0x00000078;
 817 }
 818
 819 static void pxa270a1_initfn(Object *obj)
 820 {
 821     ARMCPU *cpu = ARM_CPU(obj);
 822
 823     cpu->dtb_compatible = "marvell,xscale";
 824     set_feature(&cpu->env, ARM_FEATURE_V5);
 825     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 826     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 827     cpu->midr = 0x69054111;
 828     cpu->ctr = 0xd172172;
 829     cpu->reset_sctlr = 0x00000078;
 830 }
 831
 832 static void pxa270b0_initfn(Object *obj)
 833 {
 834     ARMCPU *cpu = ARM_CPU(obj);
 835
 836     cpu->dtb_compatible = "marvell,xscale";
 837     set_feature(&cpu->env, ARM_FEATURE_V5);
 838     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 839     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 840     cpu->midr = 0x69054112;
 841     cpu->ctr = 0xd172172;
 842     cpu->reset_sctlr = 0x00000078;
 843 }
 844
 845 static void pxa270b1_initfn(Object *obj)
 846 {
 847     ARMCPU *cpu = ARM_CPU(obj);
 848
 849     cpu->dtb_compatible = "marvell,xscale";
 850     set_feature(&cpu->env, ARM_FEATURE_V5);
 851     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 852     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 853     cpu->midr = 0x69054113;
 854     cpu->ctr = 0xd172172;
 855     cpu->reset_sctlr = 0x00000078;
 856 }
 857
 858 static void pxa270c0_initfn(Object *obj)
 859 {
 860     ARMCPU *cpu = ARM_CPU(obj);
 861
 862     cpu->dtb_compatible = "marvell,xscale";
 863     set_feature(&cpu->env, ARM_FEATURE_V5);
 864     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 865     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 866     cpu->midr = 0x69054114;
 867     cpu->ctr = 0xd172172;
 868     cpu->reset_sctlr = 0x00000078;
 869 }
 870
 871 static void pxa270c5_initfn(Object *obj)
 872 {
 873     ARMCPU *cpu = ARM_CPU(obj);
 874
 875     cpu->dtb_compatible = "marvell,xscale";
 876     set_feature(&cpu->env, ARM_FEATURE_V5);
 877     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 878     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 879     cpu->midr = 0x69054117;
 880     cpu->ctr = 0xd172172;
 881     cpu->reset_sctlr = 0x00000078;
 882 }
 883
 884 #ifdef CONFIG_USER_ONLY
 885 static void arm_any_initfn(Object *obj)
 886 {
 887     ARMCPU *cpu = ARM_CPU(obj);
 888     set_feature(&cpu->env, ARM_FEATURE_V8);
 889     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 890     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 891     set_feature(&cpu->env, ARM_FEATURE_NEON);
 892     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 893     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 894     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 895 #ifdef TARGET_AARCH64
 896     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 897 #endif
 898     cpu->midr = 0xffffffff;
 899 }
 900 #endif
 901
 902 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 903
 904 typedef struct ARMCPUInfo {
 905     const char *name;
 906     void (*initfn)(Object *obj);
 907     void (*class_init)(ObjectClass *oc, void *data);
 908 } ARMCPUInfo;
 909
 910 static const ARMCPUInfo arm_cpus[] = {
 911 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 912     { .name = "arm926",      .initfn = arm926_initfn },
 913     { .name = "arm946",      .initfn = arm946_initfn },
 914     { .name = "arm1026",     .initfn = arm1026_initfn },
 915     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 916      * older core than plain "arm1136". In particular this does not
 917      * have the v6K features.
 918      */
 919     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 920     { .name = "arm1136",     .initfn = arm1136_initfn },
 921     { .name = "arm1176",     .initfn = arm1176_initfn },
 922     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 923     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 924                              .class_init = arm_v7m_class_init },
 925     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 926     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 927     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 928     { .name = "ti925t",      .initfn = ti925t_initfn },
 929     { .name = "sa1100",      .initfn = sa1100_initfn },
 930     { .name = "sa1110",      .initfn = sa1110_initfn },
 931     { .name = "pxa250",      .initfn = pxa250_initfn },
 932     { .name = "pxa255",      .initfn = pxa255_initfn },
 933     { .name = "pxa260",      .initfn = pxa260_initfn },
 934     { .name = "pxa261",      .initfn = pxa261_initfn },
 935     { .name = "pxa262",      .initfn = pxa262_initfn },
 936     /* "pxa270" is an alias for "pxa270-a0" */
 937     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 938     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 939     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 940     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 941     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 942     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 943     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 944 #ifdef CONFIG_USER_ONLY
 945     { .name = "any",         .initfn = arm_any_initfn },
 946 #endif
 947 #endif
 948 };
 949
 950 static Property arm_cpu_properties[] = {
 951     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 952     DEFINE_PROP_END_OF_LIST()
 953 };
 954
 955 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 956 {
 957     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 958     CPUClass *cc = CPU_CLASS(acc);
 959     DeviceClass *dc = DEVICE_CLASS(oc);
 960
 961     acc->parent_realize = dc->realize;
 962     dc->realize = arm_cpu_realizefn;
 963     dc->props = arm_cpu_properties;
 964
 965     acc->parent_reset = cc->reset;
 966     cc->reset = arm_cpu_reset;
 967
 968     cc->class_by_name = arm_cpu_class_by_name;
 969     cc->do_interrupt = arm_cpu_do_interrupt;
 970     cc->dump_state = arm_cpu_dump_state;
 971     cc->set_pc = arm_cpu_set_pc;
 972     cc->gdb_read_register = arm_cpu_gdb_read_register;
 973     cc->gdb_write_register = arm_cpu_gdb_write_register;
 974 #ifndef CONFIG_USER_ONLY
 975     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
 976     cc->vmsd = &vmstate_arm_cpu;
 977 #endif
 978     cc->gdb_num_core_regs = 26;
 979     cc->gdb_core_xml_file = "arm-core.xml";
 980 }
 981
 982 static void cpu_register(const ARMCPUInfo *info)
 983 {
 984     TypeInfo type_info = {
 985         .parent = TYPE_ARM_CPU,
 986         .instance_size = sizeof(ARMCPU),
 987         .instance_init = info->initfn,
 988         .class_size = sizeof(ARMCPUClass),
 989         .class_init = info->class_init,
 990     };
 991
 992     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 993     type_register(&type_info);
 994     g_free((void *)type_info.name);
 995 }
 996
 997 static const TypeInfo arm_cpu_type_info = {
 998     .name = TYPE_ARM_CPU,
 999     .parent = TYPE_CPU,
1000     .instance_size = sizeof(ARMCPU),
1001     .instance_init = arm_cpu_initfn,
1002     .instance_finalize = arm_cpu_finalizefn,
1003     .abstract = true,
1004     .class_size = sizeof(ARMCPUClass),
1005     .class_init = arm_cpu_class_init,
1006 };
1007
1008 static void arm_cpu_register_types(void)
1009 {
1010     int i;
1011
1012     type_register_static(&arm_cpu_type_info);
1013     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
1014         cpu_register(&arm_cpus[i]);
1015     }
1016 }
1017
1018 type_init(arm_cpu_register_types)