| | 1 | /* |
| | 2 | * OpenRISC interrupt. |
| | 3 | * |
| | 4 | * Copyright (c) 2011-2012 Jia Liu <[email protected]> |
| | 5 | * |
| | 6 | * This library is free software; you can redistribute it and/or |
| | 7 | * modify it under the terms of the GNU Lesser General Public |
| | 8 | * License as published by the Free Software Foundation; either |
| | 9 | * version 2 of the License, or (at your option) any later version. |
| | 10 | * |
| | 11 | * This library is distributed in the hope that it will be useful, |
| | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| | 14 | * Lesser General Public License for more details. |
| | 15 | * |
| | 16 | * You should have received a copy of the GNU Lesser General Public |
| | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| | 18 | */ |
| | 19 | |
| | 20 | #include "cpu.h" |
| | 21 | #include "qemu-common.h" |
| | 22 | #include "exec/gdbstub.h" |
| | 23 | #include "qemu/host-utils.h" |
| | 24 | #ifndef CONFIG_USER_ONLY |
| | 25 | #include "hw/loader.h" |
| | 26 | #endif |
| | 27 | |
| | 28 | void openrisc_cpu_do_interrupt(CPUState *cs) |
| | 29 | { |
| | 30 | #ifndef CONFIG_USER_ONLY |
| | 31 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
| | 32 | CPUOpenRISCState *env = &cpu->env; |
| | 33 | |
| | 34 | env->epcr = env->pc; |
| | 35 | if (env->flags & D_FLAG) { |
| | 36 | env->flags &= ~D_FLAG; |
| | 37 | env->sr |= SR_DSX; |
| | 38 | env->epcr -= 4; |
| | 39 | } |
| | 40 | if (cs->exception_index == EXCP_SYSCALL) { |
| | 41 | env->epcr += 4; |
| | 42 | } |
| | 43 | |
| | 44 | /* For machine-state changed between user-mode and supervisor mode, |
| | 45 | we need flush TLB when we enter&exit EXCP. */ |
| | 46 | tlb_flush(env, 1); |
| | 47 | |
| | 48 | env->esr = env->sr; |
| | 49 | env->sr &= ~SR_DME; |
| | 50 | env->sr &= ~SR_IME; |
| | 51 | env->sr |= SR_SM; |
| | 52 | env->sr &= ~SR_IEE; |
| | 53 | env->sr &= ~SR_TEE; |
| | 54 | env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; |
| | 55 | env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; |
| | 56 | |
| | 57 | if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { |
| | 58 | env->pc = (cs->exception_index << 8); |
| | 59 | } else { |
| | 60 | cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); |
| | 61 | } |
| | 62 | #endif |
| | 63 | |
| | 64 | cs->exception_index = -1; |
| | 65 | } |
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