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1 | /* | |
2 | * PA-RISC emulation cpu definitions for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <[email protected]> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef HPPA_CPU_H | |
21 | #define HPPA_CPU_H | |
22 | ||
23 | #include "qemu-common.h" | |
24 | #include "cpu-qom.h" | |
25 | ||
26 | /* We only support hppa-linux-user at present, so 32-bit only. */ | |
27 | #define TARGET_LONG_BITS 32 | |
28 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
29 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
30 | ||
31 | #define CPUArchState struct CPUHPPAState | |
32 | ||
33 | #include "exec/cpu-defs.h" | |
34 | #include "fpu/softfloat.h" | |
35 | ||
36 | #define TARGET_PAGE_BITS 12 | |
37 | ||
38 | #define ALIGNED_ONLY | |
39 | #define NB_MMU_MODES 1 | |
40 | #define MMU_USER_IDX 0 | |
41 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
42 | ||
43 | #define EXCP_SYSCALL 1 | |
44 | #define EXCP_SYSCALL_LWS 2 | |
45 | #define EXCP_SIGSEGV 3 | |
46 | #define EXCP_SIGILL 4 | |
47 | #define EXCP_SIGFPE 5 | |
48 | ||
49 | /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ | |
50 | #define PSW_I 0x00000001 | |
51 | #define PSW_D 0x00000002 | |
52 | #define PSW_P 0x00000004 | |
53 | #define PSW_Q 0x00000008 | |
54 | #define PSW_R 0x00000010 | |
55 | #define PSW_F 0x00000020 | |
56 | #define PSW_G 0x00000040 /* PA1.x only */ | |
57 | #define PSW_O 0x00000080 /* PA2.0 only */ | |
58 | #define PSW_CB 0x0000ff00 | |
59 | #define PSW_M 0x00010000 | |
60 | #define PSW_V 0x00020000 | |
61 | #define PSW_C 0x00040000 | |
62 | #define PSW_B 0x00080000 | |
63 | #define PSW_X 0x00100000 | |
64 | #define PSW_N 0x00200000 | |
65 | #define PSW_L 0x00400000 | |
66 | #define PSW_H 0x00800000 | |
67 | #define PSW_T 0x01000000 | |
68 | #define PSW_S 0x02000000 | |
69 | #define PSW_E 0x04000000 | |
70 | #ifdef TARGET_HPPA64 | |
71 | #define PSW_W 0x08000000 /* PA2.0 only */ | |
72 | #else | |
73 | #define PSW_W 0 | |
74 | #endif | |
75 | #define PSW_Z 0x40000000 /* PA1.x only */ | |
76 | #define PSW_Y 0x80000000 /* PA1.x only */ | |
77 | ||
78 | #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ | |
79 | | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) | |
80 | ||
81 | /* ssm/rsm instructions number PSW_W and PSW_E differently */ | |
82 | #define PSW_SM_I PSW_I /* Enable External Interrupts */ | |
83 | #define PSW_SM_D PSW_D | |
84 | #define PSW_SM_P PSW_P | |
85 | #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ | |
86 | #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ | |
87 | #ifdef TARGET_HPPA64 | |
88 | #define PSW_SM_E 0x100 | |
89 | #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ | |
90 | #else | |
91 | #define PSW_SM_E 0 | |
92 | #define PSW_SM_W 0 | |
93 | #endif | |
94 | ||
95 | typedef struct CPUHPPAState CPUHPPAState; | |
96 | ||
97 | struct CPUHPPAState { | |
98 | target_ulong gr[32]; | |
99 | uint64_t fr[32]; | |
100 | ||
101 | target_ulong sar; | |
102 | target_ulong cr26; | |
103 | target_ulong cr27; | |
104 | ||
105 | target_long psw; /* All psw bits except the following: */ | |
106 | target_ulong psw_n; /* boolean */ | |
107 | target_long psw_v; /* in most significant bit */ | |
108 | ||
109 | /* Splitting the carry-borrow field into the MSB and "the rest", allows | |
110 | * for "the rest" to be deleted when it is unused, but the MSB is in use. | |
111 | * In addition, it's easier to compute carry-in for bit B+1 than it is to | |
112 | * compute carry-out for bit B (3 vs 4 insns for addition, assuming the | |
113 | * host has the appropriate add-with-carry insn to compute the msb). | |
114 | * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. | |
115 | */ | |
116 | target_ulong psw_cb; /* in least significant bit of next nibble */ | |
117 | target_ulong psw_cb_msb; /* boolean */ | |
118 | ||
119 | target_ulong iaoq_f; /* front */ | |
120 | target_ulong iaoq_b; /* back, aka next instruction */ | |
121 | ||
122 | target_ulong ior; /* interrupt offset register */ | |
123 | ||
124 | uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ | |
125 | float_status fp_status; | |
126 | ||
127 | /* Those resources are used only in QEMU core */ | |
128 | CPU_COMMON | |
129 | }; | |
130 | ||
131 | /** | |
132 | * HPPACPU: | |
133 | * @env: #CPUHPPAState | |
134 | * | |
135 | * An HPPA CPU. | |
136 | */ | |
137 | struct HPPACPU { | |
138 | /*< private >*/ | |
139 | CPUState parent_obj; | |
140 | /*< public >*/ | |
141 | ||
142 | CPUHPPAState env; | |
143 | }; | |
144 | ||
145 | static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) | |
146 | { | |
147 | return container_of(env, HPPACPU, env); | |
148 | } | |
149 | ||
150 | #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) | |
151 | #define ENV_OFFSET offsetof(HPPACPU, env) | |
152 | ||
153 | #include "exec/cpu-all.h" | |
154 | ||
155 | static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) | |
156 | { | |
157 | return 0; | |
158 | } | |
159 | ||
160 | void hppa_translate_init(void); | |
161 | ||
162 | #define cpu_init(cpu_model) cpu_generic_init(TYPE_HPPA_CPU, cpu_model) | |
163 | ||
164 | void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
165 | ||
166 | static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, | |
167 | target_ulong *cs_base, | |
168 | uint32_t *pflags) | |
169 | { | |
170 | *pc = env->iaoq_f; | |
171 | *cs_base = env->iaoq_b; | |
172 | *pflags = env->psw_n; | |
173 | } | |
174 | ||
175 | target_ulong cpu_hppa_get_psw(CPUHPPAState *env); | |
176 | void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); | |
177 | void cpu_hppa_loaded_fr0(CPUHPPAState *env); | |
178 | ||
179 | #define cpu_signal_handler cpu_hppa_signal_handler | |
180 | ||
181 | int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); | |
182 | int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, | |
183 | int rw, int midx); | |
184 | hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); | |
185 | int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
186 | int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
187 | void hppa_cpu_do_interrupt(CPUState *cpu); | |
188 | bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
189 | void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); | |
190 | ||
191 | #endif /* HPPA_CPU_H */ |