Git Repo - qemu.git/blame_incremental

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Commit	Line	Data
	1	/*
	2	* QEMU x86 CPU
	3	*
	4	* Copyright (c) 2012 SUSE LINUX Products GmbH
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2.1 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see
	18	* <http://www.gnu.org/licenses/lgpl-2.1.html>
	19	*/
	20	#ifndef QEMU_I386_CPU_QOM_H
	21	#define QEMU_I386_CPU_QOM_H
	22
	23	#include "qom/cpu.h"
	24	#include "cpu.h"
	25	#include "qapi/error.h"
	26
	27	#ifdef TARGET_X86_64
	28	#define TYPE_X86_CPU "x86_64-cpu"
	29	#else
	30	#define TYPE_X86_CPU "i386-cpu"
	31	#endif
	32
	33	#define X86_CPU_CLASS(klass) \
	34	OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
	35	#define X86_CPU(obj) \
	36	OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
	37	#define X86_CPU_GET_CLASS(obj) \
	38	OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
	39
	40	/**
	41	* X86CPUDefinition:
	42	*
	43	* CPU model definition data that was not converted to QOM per-subclass
	44	* property defaults yet.
	45	*/
	46	typedef struct X86CPUDefinition X86CPUDefinition;
	47
	48	/**
	49	* X86CPUClass:
	50	* @cpu_def: CPU model definition
	51	* @kvm_required: Whether CPU model requires KVM to be enabled.
	52	* @parent_realize: The parent class' realize handler.
	53	* @parent_reset: The parent class' reset handler.
	54	*
	55	* An x86 CPU model or family.
	56	*/
	57	typedef struct X86CPUClass {
	58	/< private >/
	59	CPUClass parent_class;
	60	/< public >/
	61
	62	/* Should be eventually replaced by subclass-specific property defaults. */
	63	X86CPUDefinition *cpu_def;
	64
	65	bool kvm_required;
	66
	67	DeviceRealize parent_realize;
	68	void (parent_reset)(CPUState cpu);
	69	} X86CPUClass;
	70
	71	/**
	72	* X86CPU:
	73	* @env: #CPUX86State
	74	* @migratable: If set, only migratable flags will be accepted when "enforce"
	75	* mode is used, and only migratable flags will be included in the "host"
	76	* CPU model.
	77	*
	78	* An x86 CPU.
	79	*/
	80	typedef struct X86CPU {
	81	/< private >/
	82	CPUState parent_obj;
	83	/< public >/
	84
	85	CPUX86State env;
	86
	87	bool hyperv_vapic;
	88	bool hyperv_relaxed_timing;
	89	int hyperv_spinlock_attempts;
	90	bool hyperv_time;
	91	bool check_cpuid;
	92	bool enforce_cpuid;
	93	bool expose_kvm;
	94	bool migratable;
	95	bool host_features;
	96	int64_t apic_id;
	97
	98	/* if true the CPUID code directly forward host cache leaves to the guest */
	99	bool cache_info_passthrough;
	100
	101	/* Features that were filtered out because of missing host capabilities */
	102	uint32_t filtered_features[FEATURE_WORDS];
	103
	104	/* Enable PMU CPUID bits. This can't be enabled by default yet because
	105	* it doesn't have ABI stability guarantees, as it passes all PMU CPUID
	106	* bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
	107	* capabilities) directly to the guest.
	108	*/
	109	bool enable_pmu;
	110
	111	/* in order to simplify APIC support, we leave this pointer to the
	112	user */
	113	struct DeviceState *apic_state;
	114	} X86CPU;
	115
	116	static inline X86CPU x86_env_get_cpu(CPUX86State env)
	117	{
	118	return container_of(env, X86CPU, env);
	119	}
	120
	121	#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
	122
	123	#define ENV_OFFSET offsetof(X86CPU, env)
	124
	125	#ifndef CONFIG_USER_ONLY
	126	extern struct VMStateDescription vmstate_x86_cpu;
	127	#endif
	128
	129	/**
	130	* x86_cpu_do_interrupt:
	131	* @cpu: vCPU the interrupt is to be handled by.
	132	*/
	133	void x86_cpu_do_interrupt(CPUState *cpu);
	134	bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
	135
	136	int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
	137	int cpuid, void *opaque);
	138	int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
	139	int cpuid, void *opaque);
	140	int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
	141	void *opaque);
	142	int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
	143	void *opaque);
	144
	145	void x86_cpu_get_memory_mapping(CPUState cpu, MemoryMappingList list,
	146	Error **errp);
	147
	148	void x86_cpu_dump_state(CPUState cs, FILE f, fprintf_function cpu_fprintf,
	149	int flags);
	150
	151	hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	152
	153	int x86_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	154	int x86_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	155
	156	void x86_cpu_exec_enter(CPUState *cpu);
	157	void x86_cpu_exec_exit(CPUState *cpu);
	158
	159	#endif