| | 1 | /* |
| | 2 | * Microblaze MMU emulation for qemu. |
| | 3 | * |
| | 4 | * Copyright (c) 2009 Edgar E. Iglesias |
| | 5 | * |
| | 6 | * This library is free software; you can redistribute it and/or |
| | 7 | * modify it under the terms of the GNU Lesser General Public |
| | 8 | * License as published by the Free Software Foundation; either |
| | 9 | * version 2 of the License, or (at your option) any later version. |
| | 10 | * |
| | 11 | * This library is distributed in the hope that it will be useful, |
| | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| | 14 | * Lesser General Public License for more details. |
| | 15 | * |
| | 16 | * You should have received a copy of the GNU Lesser General Public |
| | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| | 18 | */ |
| | 19 | |
| | 20 | #define MMU_R_PID 0 |
| | 21 | #define MMU_R_ZPR 1 |
| | 22 | #define MMU_R_TLBX 2 |
| | 23 | #define MMU_R_TLBLO 3 |
| | 24 | #define MMU_R_TLBHI 4 |
| | 25 | #define MMU_R_TLBSX 5 |
| | 26 | |
| | 27 | #define RAM_DATA 1 |
| | 28 | #define RAM_TAG 0 |
| | 29 | |
| | 30 | /* Tag portion */ |
| | 31 | #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ |
| | 32 | #define TLB_PAGESZ_MASK 0x00000380 |
| | 33 | #define TLB_PAGESZ(x) (((x) & 0x7) << 7) |
| | 34 | #define PAGESZ_1K 0 |
| | 35 | #define PAGESZ_4K 1 |
| | 36 | #define PAGESZ_16K 2 |
| | 37 | #define PAGESZ_64K 3 |
| | 38 | #define PAGESZ_256K 4 |
| | 39 | #define PAGESZ_1M 5 |
| | 40 | #define PAGESZ_4M 6 |
| | 41 | #define PAGESZ_16M 7 |
| | 42 | #define TLB_VALID 0x00000040 /* Entry is valid */ |
| | 43 | |
| | 44 | /* Data portion */ |
| | 45 | #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ |
| | 46 | #define TLB_PERM_MASK 0x00000300 |
| | 47 | #define TLB_EX 0x00000200 /* Instruction execution allowed */ |
| | 48 | #define TLB_WR 0x00000100 /* Writes permitted */ |
| | 49 | #define TLB_ZSEL_MASK 0x000000F0 |
| | 50 | #define TLB_ZSEL(x) (((x) & 0xF) << 4) |
| | 51 | #define TLB_ATTR_MASK 0x0000000F |
| | 52 | #define TLB_W 0x00000008 /* Caching is write-through */ |
| | 53 | #define TLB_I 0x00000004 /* Caching is inhibited */ |
| | 54 | #define TLB_M 0x00000002 /* Memory is coherent */ |
| | 55 | #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ |
| | 56 | |
| | 57 | #define TLB_ENTRIES 64 |
| | 58 | |
| | 59 | struct microblaze_mmu |
| | 60 | { |
| | 61 | /* Data and tag brams. */ |
| | 62 | uint32_t rams[2][TLB_ENTRIES]; |
| | 63 | /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ |
| | 64 | uint8_t tids[TLB_ENTRIES]; |
| | 65 | /* Control flops. */ |
| | 66 | uint32_t regs[8]; |
| | 67 | |
| | 68 | int c_mmu; |
| | 69 | int c_mmu_tlb_access; |
| | 70 | int c_mmu_zones; |
| | 71 | }; |
| | 72 | |
| | 73 | struct microblaze_mmu_lookup |
| | 74 | { |
| | 75 | uint32_t paddr; |
| | 76 | uint32_t vaddr; |
| | 77 | unsigned int size; |
| | 78 | unsigned int idx; |
| | 79 | int prot; |
| | 80 | enum { |
| | 81 | ERR_PROT, ERR_MISS, ERR_HIT |
| | 82 | } err; |
| | 83 | }; |
| | 84 | |
| | 85 | unsigned int mmu_translate(struct microblaze_mmu *mmu, |
| | 86 | struct microblaze_mmu_lookup *lu, |
| | 87 | target_ulong vaddr, int rw, int mmu_idx); |
| | 88 | uint32_t mmu_read(CPUMBState *env, uint32_t rn); |
| | 89 | void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v); |
| | 90 | void mmu_init(struct microblaze_mmu *mmu); |
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